/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the Philips LPC2378 I2S controller				*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~				*/
/*																			*/
/*	2010 Mar	ZK		Original											*/
/*	2010 May	ZK		Modified to match NXP's names						*/
/*																			*/
/****************************************************************************/

#ifndef _LPC23XX_I2S
#define _LPC23XX_I2S

struct lpc23xx_i2s {

	unsigned	dao;				// Contol for digital audio out
	unsigned	dai;				// Control for digital audio in
	unsigned	txfifo;				// Transmit FIFO
	unsigned	rxfifo;				// Receive FIFO
	unsigned	stat;				// Status
	unsigned	dma1;				// DMA config 1
	unsigned	dma2;				// DMA config 2
	unsigned	irq;				// Interrupt control
	unsigned	txrate;				// Transmit bitrate divider
	unsigned	rxrate;				// Receive bit rate divider
};

/*
*	Digital audio out control register
*/

#define	I2S_DAO_WORDWIDTH		0x0003	// Word width mask
#define	I2S_DAO_WORDWIDTH_8		0x0000	// 8 bit words
#define	I2S_DAO_WORDWIDTH_16	0x0001	// 16 bit words
#define	I2S_DAO_WORDWIDTH_32	0x0003	// 32 bit words
#define	I2S_DAO_MONO			0x0004	// Mono(1) or strereo(0)
#define	I2S_DAO_STOP			0x0008	// Disable FIFO, mute channel
#define	I2S_DAO_RESET			0x0010	// Reset the Tx channel and FIFO
#define	I2S_DAO_WS_SEL			0x0020	// Slave(1) or master(0) mode
#define	I2S_DAO_WS_PERIOD(x) ((x)/2-1)<<6)	// Word select period (NOT HALF!)
#define	I2S_DAO_MUTE			0x8000	// Mute the channel

/*
*	Digital audio in control register
*/

#define	I2S_DAI_WORDWIDTH		0x0003	// Word width mask
#define	I2S_DAI_WORDWIDTH_8		0x0000	// 8 bit words
#define	I2S_DAI_WORDWIDTH_16	0x0001	// 16 bit words
#define	I2S_DAI_WORDWIDTH_32	0x0003	// 32 bit words
#define	I2S_DAI_MONO			0x0004	// Mono(1) or strereo(0)
#define	I2S_DAI_STOP			0x0008	// Disable FIFO, mute channel
#define	I2S_DAI_RESET			0x0010	// Reset the Tx channel and FIFO
#define	I2S_DAI_WS_SEL			0x0020	// Slave(1) or master(0) mode
#define	I2S_DAI_WS_PERIOD(x) ((x)/2-1)<<6)	// Word select period (NOT HALF!)

/*
*	Status register definitions
*/

#define	I2S_STAT_IRQ			0x00001	// Interrupt pending
#define	I2S_STAT_DMAREQ1		0x00002	// DMA 1 request pending
#define	I2S_STAT_DMAREQ2		0x00004	// DMA 1 request pending
#define	I2S_STAT_RXFIFO_M		0x0f000	// RX FIFO level mask
#define	I2S_STAT_RXFIFO_S		8		// RX FIFO level right shift
#define	I2S_STAT_TXFIFO_M		0xf0000	// RX FIFO level mask
#define	I2S_STAT_TXFIFO_S		16		// RX FIFO level right shift

/*
*	DMA control register definitions
*/

#define	I2S_DMA_RX_ENABLE		0x00001	// Enable DMA for Rx
#define	I2S_DMA_TX_ENABLE		0x00002	// Enable DMA for Tx
#define	I2S_DMA_RXDEPTH(n) 	   ((n)<<8)	// Rx FIFO level to trigger DMA
#define	I2S_DMA_TXDEPTH(n) 	  ((n)<<16)	// Tx FIFO level to trigger DMA

/*
*	I2S instance
*/

static volatile struct lpc23xx_i2s * const lpc_i2s = (void *) 0xe0088000;

#endif

