/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Ramtron FM25L512 64KB SPI FRAM											*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~											*/
/*																			*/
/*	2006 May	ZK		Original											*/
/*																			*/
/****************************************************************************/

#ifndef _FM25L512_H
#define _FM25L512_H

/*
*	Commands
*	~~~~~~~~
*/

#define	FM25L512_READ		0x03		// Read data from FRAM array
#define	FM25L512_WRTE		0x02		// Write data to FRAM array
#define	FM25L512_RDSR		0x05		// Read status register
#define	FM25L512_WRSR		0x01		// Write status register
#define	FM25L512_WRDI		0x04		// Clear write enable latch
#define	FM25L512_WREN		0x06		// Set write enable latch

/*
*	Status register bits
*	~~~~~~~~~~~~~~~~~~~~
*	The block protect bits are writeable, the other bits are not.
*/

#define	FM25L512_BPM		0x0c		// Block protect status mask
#define	FM25L512_BPN		0x00		// No block is protected
#define	FM25L512_BPQ		0x04		// Upper quarter protected
#define	FM25L512_BPH		0x08		// Upper half protected
#define	FM25L512_BPF		0x0c		// Full chip is protected
#define	FM25L512_WEL		0x02		// Write enable latch is set

/*
*	Device sizes
*	~~~~~~~~~~~~
*/

#define	FM25L512_CHIP_SIZE	65536		// Size of the entire chip
#define	FM25L512_ADDR_SIZE	2			// Number of address bytes

#endif

