/****************************************************************************/
/*	Copyright (c) 2009, Bendor Research Pty. Ltd. All rights reserved.		*/
/*	This software is released under the GNU General Public License, version	*/
/*	3, with the exemptions that 1) the header files installed by this 	 	*/
/*	package can be included in closed-source code and 2) the libraries		*/
/*	built by this package can be statically linked into a closed-source 	*/
/*	binary. See the file LICENSE for the details.							*/
/*	This software is provided "AS IS", without any warranty or guarantee.	*/
/*	By using this software you acknowledge that neither Bendor Research nor	*/
/*	any of its personnel or affiliates can be held liable for any damages,	*/
/*	including, but not limited to, loss of business, loss of money, loss of */
/*	life, loss of reputation, arising out of this software being faulty or	*/
/*	not performing as advertised, even if Bendor Research was aware of such	*/
/*	faults in the software. You use this software at your own risk, any and */
/*	all liabilities that arise out of your using this software are strictly	*/
/*	yours.																	*/
/****************************************************************************/

/*
*	This file contains a classical radix-2 implementation of the fast Fourier
*	transformation, for 14 bit signed short data. Apart from accessing the
*	memory in 16-bit fashion, this code is exactly the same as the fft32c.S
*	file, you can find all the comments and everything there. This one has
*	no comments whatsoever.
*/

#include <chips/ARM/func.h>

/*
*	Register definitions, do not change them.
*/

#define	DP		r0
#define	CP		r1
#define	P2		r2
#define	RV		r3
#define	Ar		r4
#define	Ai		r5
#define	Br		r6
#define	Bi		r7
#define	Ci		r8
#define	Cr		r9
#define	N0		r10
#define	N2		P2
#define	N1		r11
#define	N3		Ar
#define	N4		r12
#define	N5		r14
#define	N6		RV

	.globl	_blm_fft16c
	afunc	fft16c
_blm_fft16c:
	stmdb	sp!,{r4-r11,lr}
	tst		RV,RV
	movne	RV,#1
	mov		N3,P2
	mov		N0,#1
	mov		N0,N0,lsl P2
	mov		N1,N0;
	mov		N5,#1
	str		P2,[sp,#-4]!
0:
	str		N3,[sp,#-4]!
	mov		N4,#0
	mov		N2,#0
1:
	cmp		N4,N0,lsr #2
	mov		Cr,N4,lsl #1
	ldrleh	Ci,[CP,Cr]
	rsble	Cr,Cr,N0,lsr #1
	ldrleh	Cr,[CP,Cr]
	subgt	Ci,N0,Cr
	ldrgth	Ci,[CP,Ci]
	subgt	Cr,Cr,N0,lsr #1
	ldrgth	Cr,[CP,Cr]
	rsbgt	Cr,Cr,#0
	tst		RV,RV
	rsbeq	Ci,Ci,#0
	add		N4,N4,N5
	movs	N6,N6,lsr #1
	mov		N6,N2
	adc		N2,N2,N2
2:
	ldr		Ar,[DP,N6,lsl #2]
	mov		Ai,Ar,asr #16
	mov		Ar,Ar,lsl #16
	mov		Ar,Ar,asr #16
	add		Br,N6,N1,lsr #1
	ldr		Br,[DP,Br,lsl #2]
	mov		Bi,Br,asr #16
	mov		Br,Br,lsl #16
	mov		Br,Br,asr #16
	sub		Ar,Ar,Br
	add		Br,Ar,Br,lsl #1
	sub		Ai,Ai,Bi
	add		Bi,Ai,Bi,lsl #1
	tst		N2,#1
	bne		3f
	movs	Ar,Ar,asr #1
	adcpl	Ar,Ar,#0
	movs	Ai,Ai,asr #1
	adcpl	Ai,Ai,#0
	movs	Br,Br,asr #1
	adcpl	Br,Br,#0
	movs	Bi,Bi,asr #1
	adcpl	Bi,Bi,#0
3:
	mov		Bi,Bi,lsl #16
	mov		Br,Br,lsl #16
	orr		Bi,Bi,Br,lsr #16
	str		Bi,[DP,N6,lsl #2]
	mul		Br,Cr,Ar
	mla		Br,Ci,Ai,Br
	movs	Br,Br,asr #15
	adcpl	Br,Br,#0
	rsb		Ar,Ar,#0
	mul		Bi,Cr,Ai
	mla		Bi,Ci,Ar,Bi
	movs	Bi,Bi,asr #15
	adcpl	Bi,Bi,#0
	mov		Bi,Bi,lsl #16
	mov		Br,Br,lsl #16
	orr		Bi,Bi,Br,lsr #16
	add		Br,N6,N1,lsr #1
	str		Bi,[DP,Br,lsl #2]
	add		N6,N6,N1
	cmp		N6,N0
	blt		2b
	movs	N2,N2,lsr #1
	movcs	RV,#1
	movcc	RV,#0
	add		N2,N2,#1
	cmp		N2,N1,lsr #1
	blt		1b
	ldr		N3,[sp],#4
	mov		N5,N5,lsl #1
	mov		N1,N1,lsr #1
	subs	N3,N3,#1
	bne		0b
	ldr		P2,[sp],#4
	mov		N1,#0
	mov		N5,#1
	orr		N5,N5,N5,lsl #8
	orr		N5,N5,N5,lsl #16
	rsb		P2,P2,#32
3:
	ldr		Ar,[DP,N1,lsl #2]
	mov		N4,N1
	add		N6,N5,N5,lsl #2
	orr		N6,N6,N6,lsl #4
	and		CP,N6,N4,lsr #1
	and		N4,N4,N6
	orr		N4,CP,N4,lsl #1
	add		N6,N5,N5,lsl #1
	orr		N6,N6,N6,lsl #4
	and		CP,N6,N4,lsr #2
	and		N4,N4,N6
	orr		N4,CP,N4,lsl #2
	add		N6,N5,N5,lsl #1
	orr		N6,N6,N6,lsl #2
	and		CP,N6,N4,lsr #4
	and		N4,N4,N6
	orr		N4,CP,N4,lsl #4
	mov		N6,#255
	orr		N6,N6,N6,lsl #16
	and		CP,N6,N4,lsr #8
	and		N4,N4,N6
	orr		N4,CP,N4,lsl #8
	mov		N4,N4,ror #16
	mov		N4,N4,lsr P2
	cmp		N1,N4
	addlt	Cr,DP,N4,lsl #2
	swplt	Ar,Ar,[Cr]
	mov		Ai,Ar,asr #16
	mov		Ar,Ar,lsl #16
	mov		Ar,Ar,asr #16
	mov		Br,#0x4000
	rsb		Bi,Br,#0
	cmp		Ar,Br
	subge	Ar,Br,#1
	cmp		Ar,Bi
	addle	Ar,Bi,#1
	cmp		Ai,Br
	subge	Ai,Br,#1
	cmp		Ai,Bi
	addle	Ai,Bi,#1
	mov		Ar,Ar,lsl #16
	mov		Ar,Ar,lsr #16
	orr		Ar,Ar,Ai,lsl #16
	str		Ar,[DP,N1,lsl #2]
	add		N1,N1,#1
	cmp		N1,N0
	blt		3b
	ldmia	sp!,{r4-r11,lr}
	bx		lr
	.endfunc

