/****************************************************************************/
/*	Copyright (c) 2009, Bendor Research Pty. Ltd. All rights reserved.		*/
/*	This software is released under the GNU General Public License, version	*/
/*	3, with the exemptions that 1) the header files installed by this 	 	*/
/*	package can be included in closed-source code and 2) the libraries		*/
/*	built by this package can be statically linked into a closed-source 	*/
/*	binary. See the file LICENSE for the details.							*/
/*	This software is provided "AS IS", without any warranty or guarantee.	*/
/*	By using this software you acknowledge that neither Bendor Research nor	*/
/*	any of its personnel or affiliates can be held liable for any damages,	*/
/*	including, but not limited to, loss of business, loss of money, loss of */
/*	life, loss of reputation, arising out of this software being faulty or	*/
/*	not performing as advertised, even if Bendor Research was aware of such	*/
/*	faults in the software. You use this software at your own risk, any and */
/*	all liabilities that arise out of your using this software are strictly	*/
/*	yours.																	*/
/****************************************************************************/

#include <chips/ARM/func.h>

/*
*	Reverses a 32-bit word.
*
*	The LSB is swapped with the MSB and in general bit n is swapped with
*	with bit 31-n, where n goes from 0 to 15.
*
*	The algorithm is the following:
*
*	unsigned bitrev( unsigned x )
*	{
*		x = ( ( x & 0x55555555 ) << 1 ) | ( ( x >> 1 ) & 0x55555555 );
*		x = ( ( x & 0x33333333 ) << 2 ) | ( ( x >> 2 ) & 0x33333333 );
*		x = ( ( x & 0x0f0f0f0f ) << 4 ) | ( ( x >> 4 ) & 0x0f0f0f0f );
*		x = ( ( x & 0x00ff00ff ) << 8 ) | ( ( x >> 8 ) & 0x00ff00ff );
*		x = ( x >> 16 ) | ( x << 16 );
*		return( x );
*	}
*/

	afunc	bitrev
	mov		r1,#1
	orr		r1,r1,r1,lsl #8
	orr		r1,r1,r1,lsl #16
	orr		r2,r1,r1,lsl #2
	orr		r2,r2,r2,lsl #4
	and		r3,r2,r0,lsr #1
	and		r0,r0,r2
	orr		r0,r3,r0,lsl #1
	orr		r1,r1,r1,lsl #1
	orr		r2,r1,r1,lsl #4
	and		r3,r2,r0,lsr #2
	and		r0,r0,r2
	orr		r0,r3,r0,lsl #2
	orr		r2,r1,r1,lsl #2
	and		r3,r2,r0,lsr #4
	and		r0,r0,r2
	orr		r0,r3,r0,lsl #4
	mov		r2,#255
	orr		r2,r2,r2,lsl #16
	and		r3,r2,r0,lsr #8
	and		r0,r0,r2
	orr		r0,r3,r0,lsl #8
	mov		r0,r0,ror #16
	bx		lr
