/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	CC1101 sub-GHz RF transceiver chip										*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~										*/
/*																			*/
/*	2006 Mar	ZK		Original											*/
/*																			*/
/****************************************************************************/

#ifndef _CC1101_H
#define _CC1101_H

/*
*	"Idiot's guide to RF Chips" register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
*	There are some registers and fields that Chipcon/TI do not detail.
*	The values for these registers are not explained in the manual but are
*	"[..] given by the SmartRF(R) Studio software", a Windows drag-and-drool
*	tool for mentally challenged engineers. It is not colourful enough to
*	be used as kindergarten entertainment software, though.
*	Some register value names have _IDIOT_ in them or end with _IDIOT,
*	these are the undocumented fields or registers.
*	The values here are for type E silicon, 915MHz, 26MHz crystal oscillator.
*	The names with suffices are for the given symbol rate, 250 for 250kb/s,
*	768 is for 76.8k, 288 is 28.8k and 096 is 9.6k.
*
*	Numerically calculated register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
*	Some register values must be numerically calculated, the calculation
*	method for these is below.
*
*	Frequency offset value
*	Calculated as: Foff = ( Fxtal * FOFFS_REG ) / 16384
*
*	Frequency multiplier
*	Calculated as: Fcarrier = ( Fxtal * FMULT_REGS ) / 65536
*
*	Intermediate frequency value
*	Calculated as: Fif = ( Fxtal * IF_REG ) / 1024
*	The tool suggests that for 250kbps 280kHz is to be used and for slower
*	baud rates 152kHz is to be used.
*
*	Symbol rate
*	Calculated as: Sr = Fxtal * ( 256 + SYRM ) * 2 ^ ( SYRE - 28 )
*
*	Channel bandwidth
*	Calculated as: Bw = Fxtal / ( ( 4 + CBWM ) / 2 ^ ( CBWE + 3 ) )
*
*	Channel separation
*	Calculated as: Cs = Fxtal * ( 256 + CSPM ) * 2 ^ ( CSPE - 18 )
*
*	Frequency deviation for FSK modulation or symbol fraction for MSK
*	Calculate as: Fdev = Fxtal * ( 8 + DEVM ) * 2 ^ ( DEVE - 17 )
*	For MSK DEVE should be 0 and DEVM is the symbol time fraction
*	that is used for the phase change.
*/

/****************************************************************************/
/*					Address definitions										*/
/****************************************************************************/

/*
*	Register addresses - registers that are the same in every mode
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_ADDR_IOCFG2		0x00	// GPIO 2 configuration register
#define	CC1101_ADDR_IOCFG1		0x01	// GPIO 1 configuration register
#define	CC1101_ADDR_IOCFG0		0x02	// GPIO 0 configuration register
#define	CC1101_ADDR_FIFOTHR		0x03	// FIFO threshold
#define	CC1101_ADDR_SYNC1		0x04	// Synchronisation word high byte
#define	CC1101_ADDR_SYNC0		0x05	// Synchronisation word low byte
#define	CC1101_ADDR_PKTLEN		0x06	// Packet length
#define	CC1101_ADDR_PKTCTRL1	0x07	// Packet automation control
#define	CC1101_ADDR_PKTCTRL0	0x08	// Packet automation control
#define	CC1101_ADDR_ADDR		0x09	// Device address
#define	CC1101_ADDR_CHANNR		0x0a	// Channel number
#define	CC1101_ADDR_FSCTRL1		0x0b	// Synthesiser IF setting
#define	CC1101_ADDR_FSCTRL0		0x0c	// Synthesiser freq. offset setting
#define	CC1101_ADDR_FREQ2		0x0d	// Frequency multiplier high byte
#define	CC1101_ADDR_FREQ1		0x0e	// Frequency multiplier middle byte
#define	CC1101_ADDR_FREQ0		0x0f	// Frequency multiplier low byte
#define	CC1101_ADDR_MDMCFG4		0x10	// Modem configuration
#define	CC1101_ADDR_MDMCFG3		0x11	// Modem configuration
#define	CC1101_ADDR_MDMCFG2		0x12	// Modem configuration
#define	CC1101_ADDR_MDMCFG1		0x13	// Modem configuration
#define	CC1101_ADDR_MDMCFG0		0x14	// Modem configuration
#define	CC1101_ADDR_DEVIATN		0x15	// Deviation
#define	CC1101_ADDR_MCSM2		0x16	// Radio control state machine conf
#define	CC1101_ADDR_MCSM1		0x17	// Radio control state machine conf
#define	CC1101_ADDR_MCSM0		0x18	// Radio control state machine conf
#define	CC1101_ADDR_FOCCFG		0x19	// Frequency offset compensation
#define	CC1101_ADDR_BSCFG		0x1a	// Bit synchron configuration
#define	CC1101_ADDR_AGCCTRL2	0x1b	// AGC control
#define	CC1101_ADDR_AGCCTRL1	0x1c	// AGC control
#define	CC1101_ADDR_AGCCTRL0	0x1d	// AGC control
#define	CC1101_ADDR_WOREVT1		0x1e	// Event timeout high byte
#define	CC1101_ADDR_WOREVT0		0x1f	// Event timeout low byte
#define	CC1101_ADDR_WORCTRL		0x20	// Wake-up on radio control
#define	CC1101_ADDR_FREND1		0x21	// Front-end configuration
#define	CC1101_ADDR_FREND0		0x22	// Front-end configuration
#define	CC1101_ADDR_FSCAL3		0x23	// Synthesiser calibration
#define	CC1101_ADDR_FSCAL2		0x24	// Synthesiser calibration
#define	CC1101_ADDR_FSCAL1		0x25	// Synthesiser calibration
#define	CC1101_ADDR_FSCAL0		0x26	// Synthesiser calibration
#define	CC1101_ADDR_RCCTRL1		0x27	// RC oscillator config
#define	CC1101_ADDR_RCCTRL0		0x28	// RC oscillator config
#define	CC1101_ADDR_FSTEST		0x29	// Frequency synthesiser test
#define	CC1101_ADDR_PTEST		0x2a	// Production test
#define	CC1101_ADDR_AGCTEST		0x2b	// AGC test
#define	CC1101_ADDR_TEST2		0x2c	// Various test parameters
#define	CC1101_ADDR_TEST1		0x2d	// Various test parameters
#define	CC1101_ADDR_TEST0		0x2e	// Various test parameters
#define	CC1101_ADDR_PATABLE		0x3e	// PA table
#define	CC1101_ADDR_FIFO		0x3f	// FIFO data

/*
*	Access qualifiers for the registers above
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_MODE_SR		0x80		// Single byte read
#define	CC1101_MODE_SW		0x00		// Single byte write
#define	CC1101_MODE_BR		0xc0		// Burst mode read
#define	CC1101_MODE_BW		0x40		// Burst mode write

/*
*	Status registers - single register read access only, no qualifiers
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_ADDR_CHIPID	0xf0		// Chip identifier
#define	CC1101_ADDR_VERNUM	0xf1		// Mask version number
#define	CC1101_ADDR_DFOEST	0xf2		// Demodulator freq. offs. estimate
#define	CC1101_ADDR_LQIEST	0xf3		// Link quality estimate
#define	CC1101_ADDR_RECSSI	0xf4		// Received signal strength
#define	CC1101_ADDR_RCSMST	0xf5		// Radio control SM state
#define	CC1101_ADDR_WORTIH	0xf6		// Wake-up on radio timer high byte
#define	CC1101_ADDR_WORTIL	0xf7		// Wake-up on radio timer low byte
#define	CC1101_ADDR_PKTSTA	0xf8		// Packet status
#define	CC1101_ADDR_PLLCAL	0xf9		// PLL calibration test status
#define	CC1101_ADDR_TXFSTA	0xfa		// Transmit FIFO status
#define	CC1101_ADDR_RXFSTA	0xfb		// Recieve FIFO status

/*
*	Address triggered commands, single access only, no qualifiers
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_CMD_SRES		0x30		// Reset chip
#define	CC1101_CMD_SONW		0x31		// Synthesiser on, go to WAIT state
#define	CC1101_CMD_SOFF		0x32		// Synthesiser off
#define	CC1101_CMD_SCAL		0x33		// Calibrate and turn off synth.
#define	CC1101_CMD_ERXS		0x34		// Enter RX state
#define	CC1101_CMD_ETXS		0x35		// Enter TX state
#define	CC1101_CMD_IDLE		0x36		// Go to IDLE state
#define	CC1101_CMD_SWOR		0x38		// Go to WOR state
#define	CC1101_CMD_SPWD		0x39		// Power down
#define	CC1101_CMD_FRXR		0x3a		// Flush receive FIFO
#define	CC1101_CMD_FTXF		0x3b		// Flush transmit FIFO
#define	CC1101_CMD_WRST		0x3c		// Reset WOR real-time clock
#define	CC1101_CMD_SNOP		0x3d		// No-op

/****************************************************************************/
/*					Status register definitions								*/
/****************************************************************************/

/*
*	The first byte from the CC1101 in every SPI transaction is the status
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	The FIFO bytes field (lower nibble) depends on whether the command byte
*	is write or read. If it is a read, then the lower nibble indicates the
*	number of data bytes available in the receive FIFO; the number 15
*	meaning that 15 or more bytes are available. If the command byte was
*	a write, then the lower nibble indicates the number of free slots in
*	the transmit FIFO; 15 means that at least 15 bytes are available.
*	The SNOP address triggered command can be used to obtain the
*	status, the SNOP can be read or written at any time and it has no
*	effect on the chip.
*/

#define	CC1101_STAT_CNRDY		0x80	// Chip is not ready
#define	CC1101_STAT_SMASK		0x70	// Status mask
#define	CC1101_STAT_FMASK		0x0f	// FIFO mask
#define	CC1101_STAT_SIDLE		0x00	// Chip is idle
#define	CC1101_STAT_SRXON		0x10	// Receive active state
#define	CC1101_STAT_STXON		0x20	// Transmit active state
#define	CC1101_STAT_SFTXR		0x30	// Fast transmit ready state
#define	CC1101_STAT_SFCAL		0x40	// Frequency calibration state
#define	CC1101_STAT_SPLLS		0x50	// PLL is settling
#define	CC1101_STAT_SRXFO		0x60	// Rx FIFO overflow
#define	CC1101_STAT_STXFU		0x70	// Tx FIFO underflow

/*
*	State machine state register
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_RCSMST_MASK		0x1f	// State mask
#define	CC1101_RCSMST_SLEEP		0x00	// Chip is in sleep mode
#define	CC1101_RCSMST_IDLE		0x01	// Chip is awake, idling
#define	CC1101_RCSMST_XOFF		0x02	// Oscillator off
#define	CC1101_RCSMST_MCS1		0x03	// Manual calibration state 1
#define	CC1101_RCSMST_MCS2		0x04	// Manual calibration state 2
#define	CC1101_RCSMST_MCS3		0x05	// Manual calibration state 3
#define	CC1101_RCSMST_WUS1		0x06	// Wake-up state 1
#define	CC1101_RCSMST_WUS2		0x07	// Wake-up state 2
#define	CC1101_RCSMST_CAL1		0x08	// Calibration state 1
#define	CC1101_RCSMST_STL1		0x09	// Settling state 1
#define	CC1101_RCSMST_STL2		0x0a	// Settling state 2
#define	CC1101_RCSMST_STL3		0x0b	// Settling state 3
#define	CC1101_RCSMST_CAL2		0x0c	// Calibration state 2
#define	CC1101_RCSMST_RX1		0x0d	// Receive state 1
#define	CC1101_RCSMST_RX2		0x0e	// Receive state 2
#define	CC1101_RCSMST_RX3		0x0f	// Receive state 3
#define	CC1101_RCSMST_TXRX		0x10	// Transiting from Tx to Rx
#define	CC1101_RCSMST_RXOF		0x11	// Receive FIFO overflow
#define	CC1101_RCSMST_FSTX		0x12	// Fast TX ready
#define	CC1101_RCSMST_TX1		0x13	// Transmit state 1
#define	CC1101_RCSMST_TX2		0x14	// Transmit state 2
#define	CC1101_RCSMST_RXTX		0x15	// Transiting from Rx to Tx
#define	CC1101_RCSMST_TXUF		0x16	// Transmit FIFO underflow

/*
*	Packet status register bit definitions
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_PKTSTA_CRC		0x80	// Last CRC matched
#define	CC1101_PKTSTA_CS		0x40	// Carrier sense
#define	CC1101_PKTSTA_PQT		0x20	// Preamble quality reached
#define	CC1101_PKTSTA_CCA		0x10	// Channel clear assesment result
#define	CC1101_PKTSTA_SFD		0x08	// Sync word found
#define	CC1101_PKTSTA_GDO2		0x04	// Status of the GDO2 pin
#define	CC1101_PKTSTA_GDO0		0x01	// Status of the GDO0 pin

/*
*	Receive FIFO status register field definitions
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_RXFSTA_FOVF		0x80	// Receive FIFO overflow
#define	CC1101_RXFSTA_FLEN		0x7f	// Receive FIFO data length

/*
*	Transmit FIFO status register field definitions
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_TXFSTA_FURF		0x80	// Transmit FIFO underflow
#define	CC1101_TXFSTA_FLEN		0x7f	// Transmit FIFO data(!) length

/*
*	Link quality estimate register field definitions
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	This is the same format as the LQI byte appended to the packet
*	(if that feature is turned on).
*/

#define	CC1101_LQIEST_CRC		0x80	// Last Rx CRC matched
#define	CC1101_LQIEST_LQI		0x7f	// Link quality estimate

/*
*	Receive signal strength register definitions
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	The macro below converts the RSSI register value to a signed
*	byte in dBm (depending on modulation mode the returned value
*	might be about 3dBm higher than reality).
*	This is the same format as the RSSI byte appended to the packet
*	(if that feature is turned on).
*/

#define	CC1101_RECSSI_dBm( x )	((int)((signed char)x+1)/2-72)

/****************************************************************************/
/*					Physical pin configuration								*/
/****************************************************************************/

/*
*	I/O pin config register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_IOCFG_RFWM		0		// Rx FIFO is above watermark
#define	CC1101_IOCFG_RFEP		1		// As above, or end of packet
#define	CC1101_IOCFG_TFWM		2		// Tx FIFO is above watermark
#define	CC1101_IOCFG_TFFL		3		// Tx FIFO full, Cleared below watermak
#define	CC1101_IOCFG_RFOF		4		// Rx FIFO overlow. Cleared by flush
#define	CC1101_IOCFG_TXUF		5		// Tx FIFO underflow. Cleared by flush
#define	CC1101_IOCFG_DATA		6		// Indicates data between SYNC and CRC
#define	CC1101_IOCFG_RCOK		7		// Rx CRC OK. Cleared by reading Rx FIFO
#define	CC1101_IOCFG_RPQR		8		// Rx preamble quality is above PQT
#define	CC1101_IOCFG_CLRC		9		// Channel is clear (RSSI < threshold)
#define	CC1101_IOCFG_LOCK		10		// Detector locked
#define	CC1101_IOCFG_SCLK		11		// Synchronous mode serial clock out
#define	CC1101_IOCFG_SRXD		12		// Synchronous mode serial data	out
#define	CC1101_IOCFG_ARXD		13		// Asynchronous mode data out
#define	CC1101_IOCFG_CSEN		14		// Carrier sense (RSSI > threshold)
#define	CC1101_IOCFG_CRCP		15		// CRC was OK. Cleared by Rx restart
#define	CC1101_IOCFG_RHD1		22		// Rx hard data 1
#define	CC1101_IOCFG_RHD0		23		// Rx hard data 0
#define	CC1101_IOCFG_PAEN		27		// Power amplifier enable
#define	CC1101_IOCFG_LNEN		28		// ??? (LNA) enable
#define	CC1101_IOCFG_TICK		29		// Rx hard data tick
#define	CC1101_IOCFG_CRDY		41		// Chip ready
#define	CC1101_IOCFG_XOSC		43		// Crystal oscillator stable
#define	CC1101_IOCFG_0TXD		45		// Transmit data input (GDO 0 only)
#define	CC1101_IOCFG_HIZ		46		// Pin is in high-imedance state
#define	CC1101_IOCFG_SET0		47		// Pin is 0 (or 1, if inverted)
#define	CC1101_IOCFG_C1			48		// Crystal oscillator /   1 out
#define	CC1101_IOCFG_C1_5		49		// Crystal oscillator /   1.5 out
#define	CC1101_IOCFG_C2			50		// Crystal oscillator /   2 out
#define	CC1101_IOCFG_C3			51		// Crystal oscillator /   3 out
#define	CC1101_IOCFG_C4			52		// Crystal oscillator /   4 out
#define	CC1101_IOCFG_C6			53		// Crystal oscillator /   6 out
#define	CC1101_IOCFG_C8			54		// Crystal oscillator /   8 out
#define	CC1101_IOCFG_C12		55		// Crystal oscillator /  12 out
#define	CC1101_IOCFG_C16		56		// Crystal oscillator /  16 out
#define	CC1101_IOCFG_C24		57		// Crystal oscillator /  24 out
#define	CC1101_IOCFG_C32		58		// Crystal oscillator /  32 out
#define	CC1101_IOCFG_C48		59		// Crystal oscillator /  48 out
#define	CC1101_IOCFG_C64		60		// Crystal oscillator /  64 out
#define	CC1101_IOCFG_C96		61		// Crystal oscillator /  96 out
#define	CC1101_IOCFG_C128		62		// Crystal oscillator / 128 out
#define	CC1101_IOCFG_C192		63		// Crystal oscillator / 196 out

#define	CC1101_IOCFG_INV		0x40	// Invert the signal on the pin
#define	CC1101_IDCFG0_TEMP		0x80	// GDO0, enables the temperature sensor
#define	CC1101_IDCFG1_HDRV		0x80	// GDO1, high drive strength on pins

/****************************************************************************/
/*					Control state machine configuration						*/
/****************************************************************************/

/*
*	State machine control register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	PQI is preamble quality indicator
*	Ftx is fast transmit (ready to transmit, with carrier on)
*/

#define CC1101_MCSM2_RSSI		0x10	// Rx SM timeout in low RSSI
#define CC1101_MCSM2_QSYN		0x00	// Quialifier is sync word only
#define CC1101_MCSM2_QSOP		0x08	// Qualifier sync word or PQI
#define CC1101_MCSM2_TIME(n) ((n)-3)	// Rx timeout divider exponent 3-9
#define CC1101_MCSM2_TINF 		0x07	// No Rx timeout (infinite timeout)

#define CC1101_MCSM1_CCNC		0x00	// Clear channel is not checked
#define CC1101_MCSM1_CCSS		0x10	// Clear channel is RSSI based
#define CC1101_MCSM1_CCRX		0x20	// If no Rx is in progress
#define CC1101_MCSM1_CCRS		0x30	// If no Rx in progress then RSSI
#define CC1101_MCSM1_REID		0x00	// At end of Rx packet go to idle
#define CC1101_MCSM1_REFS		0x04	// At end of Rx packet go to Ftx
#define CC1101_MCSM1_RETX		0x08	// At end of Rx packet go to Tx
#define CC1101_MCSM1_RERX		0x0c	// At end of Rx packet stay in Rx
#define CC1101_MCSM1_TEID		0x00	// At end of Tx packet go to idle
#define CC1101_MCSM1_TEFS		0x01	// At end of Tx packet go to Ftx
#define CC1101_MCSM1_TETX		0x02	// At end of Tx packet stay in Tx
#define CC1101_MCSM1_TERX		0x03	// At end of Tx packet go to Rx

#define CC1101_MCSM0_SCAL		0x00	// Autocal only on SCAL strobe
#define CC1101_MCSM0_TORT		0x10	// Autocal when going to Rx or Tx
#define CC1101_MCSM0_TOID		0x20	// Autocal when going to idle
#define CC1101_MCSM0_TO4I		0x30	// At every 4th time going to idle
#define CC1101_MCSM0_RT2		0x00	// Chip ready timeout ~2.5us
#define CC1101_MCSM0_RT40		0x04	// Chip ready timeout ~40us
#define CC1101_MCSM0_RT153		0x08	// Chip ready timeout ~153us
#define CC1101_MCSM0_RT635		0x0c	// Chip ready timeout ~635us
#define CC1101_MCSM0_RCPE		0x02	// Radio control pin enable
#define CC1101_MCSM0_SPOO		0x01	// In sleep mode xtal osc stays on

/*
*	Wake-up on radio control register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define CC1101_WORCTRL_RCOF		0x80	// Power down the RC oscillator
#define CC1101_WORCTRL_E1T4		0x00	// Event 1 timeout  4 clocks
#define CC1101_WORCTRL_E1T6		0x10	// Event 1 timeout  6 clocks
#define CC1101_WORCTRL_E1T8		0x20	// Event 1 timeout  8 clocks
#define CC1101_WORCTRL_E1T12	0x30	// Event 1 timeout 12 clocks
#define CC1101_WORCTRL_E1T16	0x40	// Event 1 timeout 16 clocks
#define CC1101_WORCTRL_E1T24	0x50	// Event 1 timeout 24 clocks
#define CC1101_WORCTRL_E1T32	0x60	// Event 1 timeout 32 clocks
#define CC1101_WORCTRL_E1T48	0x70	// Event 1 timeout 48 clocks
#define CC1101_WORCTRL_E0R1		0x00	// Event0 resolution 2^1 periods
#define CC1101_WORCTRL_E0R5		0x01	// Event0 resolution 2^5 periods
#define CC1101_WORCTRL_E0R10	0x02	// Event0 resolution 2^10 periods
#define CC1101_WORCTRL_E0R15	0x03	// Event0 resolution 2^15 periods

/****************************************************************************/
/*					Modem and data interface configuration					*/
/****************************************************************************/

/*
*	Modem config register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	It should be noted that the 1.1 revision of the manual states that
*	forward error correction should only be used with fixed packet length.
*	The 1.0 version of the manual omits this comment.
*	It seems that error correction works with max packet length mode as well.
*/

#define CC1101_MDMCFG4_CBWE(n) ((n)<<6)	// Channel bandwidth exponent 0-3
#define CC1101_MDMCFG4_CBWM(n) ((n)<<4)	// Channel bandwidth mantissa 0-3
#define CC1101_MDMCFG4_SYRE(n) 	(n)		// Symbol rate exponent 0-15

#define CC1101_MDMCFG3_SYRM(n) 	(n)		// Symbol rate exponent 0-255

#define CC1101_MDMCFG2_DFOF		0x80	// Demod DC filter off
#define CC1101_MDMCFG2_DFON		0x00	// Demod DC filter on
#define CC1101_MDMCFG2_2FSK		0x00	// 2-FSK modulation
#define CC1101_MDMCFG2_GFSK		0x10	// GFSK modulation
#define CC1101_MDMCFG2_ASK		0x30	// ASK modulation
#define CC1101_MDMCFG2_4FSK		0x40	// 4-FSK modulation
#define CC1101_MDMCFG2_MSK		0x70	// MSK modulation
#define CC1101_MDMCFG2_MANC		0x08	// Manchester enabled

#define CC1101_MDMCFG2_CSEN		0x04	// Carrier sense enabled
#define CC1101_MDMCFG2_NOSY		0x00	// No sync (or preamble) is needed
#define CC1101_MDMCFG2_SY15		0x01	// 16 bit sync, 15 must match
#define CC1101_MDMCFG2_SY16		0x02	// 16 bit sync, 16 must match
#define CC1101_MDMCFG2_SY30		0x03	// 32 bit sync, 30 must match

#define CC1101_MDMCFG1_FECE		0x80	// Enable forward error correction
#define CC1101_MDMCFG1_PR2		0x00	// Tx 2 bytes of preamble
#define CC1101_MDMCFG1_PR3		0x10	// Tx 3 bytes of preamble
#define CC1101_MDMCFG1_PR4		0x20	// Tx 4 bytes of preamble
#define CC1101_MDMCFG1_PR6		0x30	// Tx 6 bytes of preamble
#define CC1101_MDMCFG1_PR8		0x40	// Tx 8 bytes of preamble
#define CC1101_MDMCFG1_PR12		0x50	// Tx 12 bytes of preamble
#define CC1101_MDMCFG1_PR16		0x60	// Tx 16 bytes of preamble
#define CC1101_MDMCFG1_PR24		0x70	// Tx 24 bytes of preamble
#define CC1101_MDMCFG1_CSPE(n)	(n)		// Channel spacing exponent 0-3

#define CC1101_MDMCFG0_CSPM(n)	(n)		// Channel spacing mantissa 0-255

#define CC1101_DEVIATN_DEVE(n) ((n)<<4)	// Deviation exponent 0-3
#define CC1101_DEVIATN_DEVM(n) 	(n)		// Deviation mantissa 0-3

/*
*	Bit synchroniser control register
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_BSCFG_CRLI_1		0x00	// Feedback integral gain 1
#define	CC1101_BSCFG_CRLI_2		0x40	// Feedback integral gain 2
#define	CC1101_BSCFG_CRLI_3		0x80	// Feedback integral gain 3
#define	CC1101_BSCFG_CRLI_4		0xc0	// Feedback integral gain 4
#define	CC1101_BSCFG_CRLP_1		0x00	// Feedback proportional gain 1
#define	CC1101_BSCFG_CRLP_2		0x10	// Feedback proportional gain 1
#define	CC1101_BSCFG_CRLP_3		0x20	// Feedback proportional gain 1
#define	CC1101_BSCFG_CRLP_4		0x30	// Feedback proportional gain 1

#define	CC1101_BSCFG_HALFI		0x08	// After sync halve integral gain
#define	CC1101_BSCFG_HALFP		0x04	// After sync halve proport. gain

#define	CC1101_BSCFG_COMP_0		0x00	// No rate offset compensation
#define	CC1101_BSCFG_COMP_3		0x01	// 3.125% data rate offset comp.
#define	CC1101_BSCFG_COMP_6		0x02	// 6.250% data rate offset comp.
#define	CC1101_BSCFG_COMP_12	0x03	// 12.50% data rate offset comp.

/*
*	Packet automation control register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_PKTCTRL1_PQT(n)  ((n)<<5)	// Preamble quality threshold 0-7
#define	CC1101_PKTCTRL1_WASY		0x10	// WOR autosync	enable
#define	CC1101_PKTCTRL1_ASTA		0x04	// Appends status to payload
#define	CC1101_PKTCTRL1_NOAC		0x00	// No address check
#define	CC1101_PKTCTRL1_OWNO		0x01	// Only own address is accepted
#define	CC1101_PKTCTRL1_OAB0		0x02	// Own address and 0x00	accepted
#define	CC1101_PKTCTRL1_O0FF		0x03	// Own address and 0x00 or 0xFF

#define	CC1101_PKTCTRL0_WHIT		0x40	// Data whitening on
#define	CC1101_PKTCTRL0_NORM		0x00	// Normal (FIFO based) mode
#define	CC1101_PKTCTRL0_SYNC		0x10	// Synchronous mode (on GPOs)
#define	CC1101_PKTCTRL0_RAND		0x20	// Random Tx, normal Rx mode
#define	CC1101_PKTCTRL0_ASYN		0x30	// Asynchrounous mode (on GPOs)
#define	CC1101_PKTCTRL0_2400		0x08	// CC2400 CRC support
#define	CC1101_PKTCTRL0_CRCE		0x04	// CRC generator enabled
#define	CC1101_PKTCTRL0_FIXL		0x00	// Packets are fixed length
#define	CC1101_PKTCTRL0_MAXL		0x01	// Packet length has a max value
#define	CC1101_PKTCTRL0_INFL		0x02	// Infinite packet length

/*
*	FIFO threshold register fields
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	The first number in the name is the Tx threshold, second is the Rx
*/

#define	CC1101_FIFOTHR_61_4			0
#define	CC1101_FIFOTHR_57_8			1
#define	CC1101_FIFOTHR_53_12		2
#define	CC1101_FIFOTHR_49_16		3
#define	CC1101_FIFOTHR_45_20		4
#define	CC1101_FIFOTHR_41_24		5
#define	CC1101_FIFOTHR_37_28		6
#define	CC1101_FIFOTHR_33_32		7
#define	CC1101_FIFOTHR_29_36		8
#define	CC1101_FIFOTHR_25_40		9
#define	CC1101_FIFOTHR_21_44		10
#define	CC1101_FIFOTHR_17_48		11
#define	CC1101_FIFOTHR_13_52		12
#define	CC1101_FIFOTHR_9_56			13
#define	CC1101_FIFOTHR_5_60			14
#define	CC1101_FIFOTHR_1_64			15

/****************************************************************************/
/*					RF section configuration								*/
/****************************************************************************/

/*
*	Frequency compensation control
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

#define	CC1101_FOCCFG_GATE		0x20	// Carrier sense gates compensation
#define	CC1101_FOCCFG_GAIN_1	0x00	// Feedback gain is	1
#define	CC1101_FOCCFG_GAIN_2	0x08	// Feedback gain is	2
#define	CC1101_FOCCFG_GAIN_3	0x10	// Feedback gain is	3
#define	CC1101_FOCCFG_GAIN_4	0x18	// Feedback gain is	4
#define	CC1101_FOCCFG_HALF		0x04	// Halve gain after sync word
#define	CC1101_FOCCFG_COMP_0	0x00	// No frequency compensation
#define	CC1101_FOCCFG_COMP_8	0x01	// Max. comp. is chan. bandwidth/8
#define	CC1101_FOCCFG_COMP_4	0x02	// Max. comp. is chan. bandwidth/4
#define	CC1101_FOCCFG_COMP_2	0x03	// Max. comp. is chan. bandwidth/2

/*
*	AGC control registers
*	~~~~~~~~~~~~~~~~~~~~~
*
*	The LNA (Low-Noise Amplifier, the actual high-frequency amplifier) has
*	two stages. Both of them are variable gain. You can choose which one
*	will have its gain decreased first when the signal strength is too high.
*
*	The DVGA (Digital Variable Gain Amplifier) is an other amplifier
*	(probably) that you can control to some degree.
*
*	Further, the carrier sense circuit can be controlled by the AGC
*	registers.
*
*	The AGCCTRL0_HYST_ field controls the AGC's own internal decision
*	logic (not much detail is available, the SW tool sets it to medium).
*
*	The AGCCTRL0_WAIT_ field is the delay after a gain adjustment before
*	the AGC start to measure the input again.
*
*	The AGCCTRL0_FRZE_ controls the freezing of the AGC operation. You can
*	force the AGC to stop changing the gain of the analogue and/or the
*	digital amplifiers.
*
*	The AGCCTRL0_SAMP_ field sets the length of the averaging filter within
*	the AGC. It also affects the decision boundary for ASK modulation.
*
*	The AGCCTRL1_LNA_ field controls which stage of the LNA is controlled
*	first. The other stage is controlled only if the selected stage is
*	already at the minimum gain.
*
*	The AGCCTRL1_CSRT_ controls the relative threshold for carrier sense.
*	Carrier sense will be asserted if the RSSI jumps by the given amount.
*
*	The AGCCTRL1_CSAT_ controls the absolute threshold for carrier sense.
*	Carrier sense will be asserted if the RSSI value is greater than
*	MAGN_TARGET - MAX_GAIN + AGCCTRL1_CSAT. In this context MAX GAIN is
*	MAX_DVGA_GAIN + MAX_LNA_GAIN, fields of AGCCTRL2.
*
*	The AGCCTRL2_DVGA controls the maximum amplification in the DVGA.
*	The absolute value is not given in the manual, but whatever it
*	is, it can be reduced by 6, 12 or 18dB.
*
*	The AGCCTRL2_LNA controls the max. LNA gain. Again, the actual
*	max value is not known, but it can be reduced by up to 17dB.
*
*	The AGCCTRL2_TAMP sets the target amplitude from the digital
*	filter between 24 and 42dB. What exactly this means is still
*	black magic, but at least something to play with...
*	We know, however, that the higher this value is, the less
*	headroom is available for blockers (i.e. close range selectivity
*	goes down).
*/

#define	CC1101_AGCCTRL2_DVGA_MSK	0xc0	// DVGA max. gain
#define	CC1101_AGCCTRL2_DVGA_00		0x00	// DVGA max. gain is not limited
#define	CC1101_AGCCTRL2_DVGA_06		0x40	// DVGA max. gain decreased by  6dB
#define	CC1101_AGCCTRL2_DVGA_12		0x80	// DVGA max. gain decreased by 12dB
#define	CC1101_AGCCTRL2_DVGA_18		0xc0	// DVGA max. gain decreased by 18dB

#define	CC1101_AGCCTRL2_LNA_MSK		0x38	// LNA max gain
#define	CC1101_AGCCTRL2_LNA_0		0x00	// LNA max gain is not limited
#define	CC1101_AGCCTRL2_LNA_026		0x08	// LNA max gain decreased by  2.6dB
#define	CC1101_AGCCTRL2_LNA_061		0x10	// LNA max gain decreased by  6.1dB
#define	CC1101_AGCCTRL2_LNA_074		0x18	// LNA max gain decreased by  7.4dB
#define	CC1101_AGCCTRL2_LNA_092		0x20	// LNA max gain decreased by  9.2dB
#define	CC1101_AGCCTRL2_LNA_115		0x28	// LNA max gain decreased by 11.5dB
#define	CC1101_AGCCTRL2_LNA_146		0x30	// LNA max gain decreased by 14.6dB
#define	CC1101_AGCCTRL2_LNA_171		0x38	// LNA max gain decreased by 17.1dB

#define	CC1101_AGCCTRL2_TAMP_MSK	0x07	// Target amplitude mask
#define	CC1101_AGCCTRL2_TAMP_24		0x00	// Target amplitude is 24dBm
#define	CC1101_AGCCTRL2_TAMP_27		0x01	// Target amplitude is 27dBm
#define	CC1101_AGCCTRL2_TAMP_30		0x02	// Target amplitude is 30dBm
#define	CC1101_AGCCTRL2_TAMP_33		0x03	// Target amplitude is 33dBm
#define	CC1101_AGCCTRL2_TAMP_36		0x04	// Target amplitude is 36dBm
#define	CC1101_AGCCTRL2_TAMP_38		0x05	// Target amplitude is 38dBm
#define	CC1101_AGCCTRL2_TAMP_40		0x06	// Target amplitude is 40dBm
#define	CC1101_AGCCTRL2_TAMP_42		0x07	// Target amplitude is 42dBm

#define	CC1101_AGCCTRL1_LNA_STG1	0x40	// AGC controls stage 1 first
#define	CC1101_AGCCTRL1_LNA_STG2	0x00	// AGC controls stage 2 first

#define	CC1101_AGCCTRL1_CSRT_MSK	0x30	// Carrier sense relative threshold
#define	CC1101_AGCCTRL1_CSRT_DIS	0x00	// Carrier sense threshold disabled
#define	CC1101_AGCCTRL1_CSRT_06		0x10	//  6dB jump in RSSI
#define	CC1101_AGCCTRL1_CSRT_10		0x20	// 10dB jump in RSSI
#define	CC1101_AGCCTRL1_CSRT_14		0x30	// 14dB jump in RSSI

#define	CC1101_AGCCTRL1_CSAT_MSK	0x0f	// Carrier sense absolute threshold
#define	CC1101_AGCCTRL1_CSAT_DIS	0x08	// Carrier sense threshold disabled
#define	CC1101_AGCCTRL1_CSAT_m7		0x09	// -7dB
#define	CC1101_AGCCTRL1_CSAT_m6		0x0a	// -6dB
#define	CC1101_AGCCTRL1_CSAT_m5		0x0b	// -5dB
#define	CC1101_AGCCTRL1_CSAT_m4		0x0c	// -4dB
#define	CC1101_AGCCTRL1_CSAT_m3		0x0d	// -3dB
#define	CC1101_AGCCTRL1_CSAT_m2		0x0e	// -2dB
#define	CC1101_AGCCTRL1_CSAT_m1		0x0f	// -1dB
#define	CC1101_AGCCTRL1_CSAT_0		0x00	//  0dB
#define	CC1101_AGCCTRL1_CSAT_p1		0x01	// +1dB
#define	CC1101_AGCCTRL1_CSAT_p2		0x02	// +2dB
#define	CC1101_AGCCTRL1_CSAT_p3		0x03	// +3dB
#define	CC1101_AGCCTRL1_CSAT_p4		0x04	// +4dB
#define	CC1101_AGCCTRL1_CSAT_p5		0x05	// +5dB
#define	CC1101_AGCCTRL1_CSAT_p6		0x06	// +6dB
#define	CC1101_AGCCTRL1_CSAT_p7		0x07	// +7dB

#define	CC1101_AGCCTRL0_HYST_NO		0x00	// No hysteresis, high gain
#define	CC1101_AGCCTRL0_HYST_LO		0x40	// Low hysteresis, medium gain
#define	CC1101_AGCCTRL0_HYST_ME		0x80	// Medium hysteresis, medium gain
#define	CC1101_AGCCTRL0_HYST_HI		0xc0	// Large hysteresis, low gain

#define	CC1101_AGCCTRL0_WAIT_8		0x00	//  8 samples before AGC works
#define	CC1101_AGCCTRL0_WAIT_16		0x10	// 16 samples before AGC works
#define	CC1101_AGCCTRL0_WAIT_24		0x20	// 24 samples before AGC works
#define	CC1101_AGCCTRL0_WAIT_32		0x30	// 32 samples before AGC works

#define	CC1101_AGCCTRL0_FRZE_NO		0x00	// Continuous AGC, no freeze
#define	CC1101_AGCCTRL0_FRZE_PS		0x04	// Freeze AGC after sync word
#define	CC1101_AGCCTRL0_FRZE_AN		0x08	// Freeze analogue, leave dig. now
#define	CC1101_AGCCTRL0_FRZE_AD		0x0c	// Freeze both anal. and dig. now

#define	CC1101_AGCCTRL0_SAMP_8		0x00	// AGC filter is  8 samples
#define	CC1101_AGCCTRL0_SAMP_16		0x01	// AGC filter is 16 samples
#define	CC1101_AGCCTRL0_SAMP_32		0x02	// AGC filter is 32 samples
#define	CC1101_AGCCTRL0_SAMP_64		0x03	// AGC filter is 64 samples

/*
*	Frequency calibration registers
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	The way the frequency calibration works is that first you have to set
*	the base frequency using the FREQMx registers. You also set the
*	FSCTRL0 register and the CHANNO register.
*	Then you do a frequency calibration (or it is automatically done for
*	you). The calibration is controlled by the FSCAL3 register and the.
*	FSCAL0 register.
*	The calibration result is stored in FSCAL3 - FSCAL1. If you now
*	store these values, then if you move to an other channel and want
*	to come back, you do not have to re-calibrate the frequency (it takes
*	almost 800us to do so), it is enough if you restore the values in the
*	FSCAL3 - 1 registers. In that case the PLL settles in about 90us.
*	The FSCAL3 register, which controls the calibration contains some
*	silicon dependent magic. The lower nibble is 4 bits of the result,
*	the upper nibble is divided into 2 2-bit fields, controlling the
*	calibration configuration (bits 7-6) and the charge pump of some
*	unspecified unit on the chip (bits 5-4). Therefore, the register
*	description only gives an 'IDIOT' value, which is given by the
*	SW. The values below are for 915MHz operation, with different
*	baud rates.
*	The meaning of the value written to the FSCAL0 register is not
*	described in the manual at all, the value below is what the
*	tool gave for 915MHz.
*/

#define	CC1101_FSCAL3_CONF_MSK	0xc0
#define	CC1101_FSCAL3_PUMP_MSK	0x30

#define	CC1101_FSCAL3_IDIOT_250	0xea	// Idiot's guide to CC1101 value
#define	CC1101_FSCAL3_IDIOT_768	0xea	// Idiot's guide to CC1101 value
#define	CC1101_FSCAL3_IDIOT_288	0xa9	// Idiot's guide to CC1101 value
#define	CC1101_FSCAL3_IDIOT_096	0xa9	// Idiot's guide to CC1101 value

#define	CC1101_FSCAL0_IDIOT		0x11	// Idiot's guide to CC1101 value

/*
*	Front-end Tx configuration
*	~~~~~~~~~~~~~~~~~~~~~~~~~~
*	Similarly to the FSCAL3 register, the manual tells you the fields but
*	it does not tell you the meaning of the values, it rather suggest you
*	to use the Windows program they supply to get the value. If the field
*	comments do not make sense then be assured that they have been copied
*	from the manual verbaitm...
*	The values below are for 915MHz.
*/

#define	CC1101_FREND1_LNAC_MSK	0xc0	// Adjust LNA current
#define	CC1101_FREND1_PTAT_MSK	0x30	// Adjust front-end PTAT outputs
#define	CC1101_FREND1_RXLO_MSK	0x0c	// Adjust current RX LO buffer
#define	CC1101_FREND1_MIXC_MSK	0x03	// Adjust current in mixer

#define	CC1101_FREND1_IDIOT_768	0x86	// Idiot's guide to CC1101 value
#define	CC1101_FREND1_IDIOT_250	0x86	// Idiot's guide to CC1101 value
#define	CC1101_FREND1_IDIOT_288	0x56	// Idiot's guide to CC1101 value
#define	CC1101_FREND1_IDIOT_096	0x56	// Idiot's guide to CC1101 value

#define	CC1101_FREND0_TXLO_MSK	0x30	// Adjust current TX LO buffer
#define	CC1101_FREND0_PSEL(n)	(n)		// PA table index 0-7

#define	CC1101_FREND0_IDIOT		0x10	// Idiot's guide to CC1101 value

#endif

