/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the Philips LPC23xx timer modules				*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~				*/
/*																			*/
/*	2010 Mar	ZK		Original											*/
/*	2010 May	ZK		Modified to match NXP's names						*/
/*																			*/
/****************************************************************************/

#ifndef _LPC23xx_TIM
#define _LPC23xx_TIM

/*
*	LPC23xx timer registers
*/

struct	lpc23xx_tim {

	unsigned	ir;				// Pending interrupts
	unsigned	tcr;			// Timer control
	unsigned	tc;				// Free-running counter
	unsigned	pr;				// Prescaler upper count value
	unsigned	pc;				// Prescaler counter clocked from PCLK
	unsigned	mcr;			// Match control
	unsigned	mr[ 4 ];		// Match values
	unsigned	ccr;			// Input capture control
	unsigned	cr[ 2 ];		// Captured values
	unsigned	_[2];
	unsigned	emr;			// External match pin control
	unsigned	ctcr;			// Count control
};

/*
*	Definitions for the ir register
*/

#define	TIM_IR_MR0		0x01		// Interrupt flag for match 0
#define	TIM_IR_MR1		0x02		// Interrupt flag for match 1
#define	TIM_IR_MR2		0x04		// Interrupt flag for match 2
#define	TIM_IR_MR3		0x08		// Interrupt flag for match 3
#define	TIM_IR_CR0		0x10		// Interrupt flag for capture 0
#define	TIM_IR_CR1		0x20		// Interrupt flag for capture 0

/*
*	Definitions for the tcr register
*/

#define	TIM_TCR_ENABLE	0x01		// Counter is enabled
#define	TIM_TCR_RESET	0x02		// Counter and prescaler held in reset

/*
*	Definitions for the ctcr register
*/

#define	TIM_CTCR_PCLK	0x00		// Counter counts PCLK
#define	TIM_CTCR_RISE	0x01		// Counter counts rising edges of CAP
#define	TIM_CTCR_FALL	0x02		// Counter counts falling edges of CAP
#define	TIM_CTCR_BOTH	0x03		// Counter counts both edges of CAP
#define	TIM_CTCR_CAP0	0x00		// CAP is from channel capture input 0
#define	TIM_CTCR_CAP1	0x04		// CAP is from channel capture input 1

/*
*	Definitions for the mcr register
*/

#define	TIM_MCR_MR0I	0x001		// IRQ on match 0
#define	TIM_MCR_MR0R	0x002		// Reset counter on match 0
#define	TIM_MCR_MR0S	0x004		// Stop prescaler & counter on match 0
#define	TIM_MCR_MR1I	0x008		// IRQ on match 1
#define	TIM_MCR_MR1R	0x010		// Reset counter on match 1
#define	TIM_MCR_MR1S	0x020		// Stop prescaler & counter on match 1
#define	TIM_MCR_MR2I	0x040		// IRQ on match 2
#define	TIM_MCR_MR2R	0x080		// Reset counter on match 2
#define	TIM_MCR_MR2S	0x100		// Stop prescaler & counter on match 2
#define	TIM_MCR_MR3I	0x200		// IRQ on match 3
#define	TIM_MCR_MR3R	0x400		// Reset counter on match 3
#define	TIM_MCR_MR3S	0x800		// Stop prescaler & counter on match 3

/*
*	Definitions for the CCR register
*/

#define	TIM_CCR_CAP0RE	0x001		// Capture 0 on rising edge
#define	TIM_CCR_CAP0FE	0x002		// Capture 0 on falling edge
#define	TIM_CCR_CAP0I	0x004		// Capture 0 generates interrupt
#define	TIM_CCR_CAP1RE	0x008		// Capture 1 on rising edge
#define	TIM_CCR_CAP1FE	0x010		// Capture 1 on falling edge
#define	TIM_CCR_CAP1I	0x020		// Capture 1 generates interrupt

/*
*	Definitions for the emr register
*/

#define	TIM_EMR_EM0		0x001		// Channel 0 match controls its pin
#define	TIM_EMR_EM1		0x002		// Channel 1 match controls its pin
#define	TIM_EMR_EM2		0x004		// Channel 2 match controls its pin
#define	TIM_EMR_EM3		0x008		// Channel 3 match controls its pin
#define	TIM_EMR_EMC0M	0x030		// Channel 0 activity mask
#define	TIM_EMR_EMC0(n) ((n)<<4)	// Channel 0 activity on match
#define	TIM_EMR_EMC1M	0x0c0		// Channel 1 activity mask
#define	TIM_EMR_EMC1(n) ((n)<<6)	// Channel 1 activity on match
#define	TIM_EMR_EMC2M	0x300		// Channel 2 activity mask
#define	TIM_EMR_EMC2(n) ((n)<<8)	// Channel 2 activity on match
#define	TIM_EMR_EMC3M	0xc00		// Channel 3 activity mask
#define	TIM_EMR_EMC3(n) ((n)<<10)	// Channel 3 activity on match

#define	TIM_EMC_NOP		0			// No action
#define	TIM_EMC_CLR		1			// Clear the pin
#define	TIM_EMC_SET		2			// Set the pin
#define	TIM_EMC_TGL		3			// Toggle the pin

/*
*	Timer instances
*/

static volatile struct lpc23xx_tim * const lpc_tim0 = (void *) 0xe0004000;
static volatile struct lpc23xx_tim * const lpc_tim1 = (void *) 0xe0008000;
static volatile struct lpc23xx_tim * const lpc_tim2 = (void *) 0xe0070000;
static volatile struct lpc23xx_tim * const lpc_tim3 = (void *) 0xe0074000;

#endif

