/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the Philips LPC210x timer modules				*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~				*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC23xx version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210x_TIM
#define _LPC210x_TIM

/*
*	LPC210x timer registers
*/

struct	lpc210x_tim {

	unsigned	ir;				// 000 Pending interrupts
	unsigned	tcr;			// 004 Timer control
	unsigned	tc;				// 008 Free-running counter
	unsigned	pr;				// 00c Prescaler upper count value
	unsigned	pc;				// 010 Prescaler counter clocked from PCLK
	unsigned	mcr;			// 014 Match control
	unsigned	mr[ 4 ];		// 018 Match values
	unsigned	ccr;			// 028 Input capture control
	unsigned	cr[ 4 ];		// 02c Captured values
	unsigned	emr;			// 03c External match pin control
	unsigned	_1[12];
	unsigned	ctcr;			// 070 Count control
	unsigned	pwmcon;			// 074 PWM mode control
};

/*
*	Definitions for the ir register
*/

#define	TIM_IR_MR0		0x01		// Interrupt flag for match 0
#define	TIM_IR_MR1		0x02		// Interrupt flag for match 1
#define	TIM_IR_MR2		0x04		// Interrupt flag for match 2
#define	TIM_IR_MR3		0x08		// Interrupt flag for match 3
#define	TIM_IR_CR0		0x10		// Interrupt flag for capture 0
#define	TIM_IR_CR1		0x20		// Interrupt flag for capture 1
#define	TIM_IR_CR2		0x20		// Interrupt flag for capture 2
#define	TIM_IR_CR3		0x20		// Interrupt flag for capture 3

/*
*	Definitions for the tcr register
*/

#define	TIM_TCR_ENABLE	0x01		// Counter is enabled
#define	TIM_TCR_RESET	0x02		// Counter and prescaler held in reset

/*
*	Definitions for the ctcr register
*/

#define	TIM_CTCR_PCLK	0x00		// Counter counts PCLK
#define	TIM_CTCR_RISE	0x01		// Counter counts rising edges of CAP
#define	TIM_CTCR_FALL	0x02		// Counter counts falling edges of CAP
#define	TIM_CTCR_BOTH	0x03		// Counter counts both edges of CAP
#define	TIM_CTCR_CAP(n)	((n)<<2)	// CAP channel select
#define	TIM_CTCR_CAP_M	0x0c		// CAP mask
#define	TIM_CTCR_CAP_S	0x02		// CAP shift

/*
*	Definitions for the mcr register
*/

#define	TIM_MCR_MR0I	0x001		// IRQ on match 0
#define	TIM_MCR_MR0R	0x002		// Reset counter on match 0
#define	TIM_MCR_MR0S	0x004		// Stop prescaler & counter on match 0
#define	TIM_MCR_MR1I	0x008		// IRQ on match 1
#define	TIM_MCR_MR1R	0x010		// Reset counter on match 1
#define	TIM_MCR_MR1S	0x020		// Stop prescaler & counter on match 1
#define	TIM_MCR_MR2I	0x040		// IRQ on match 2
#define	TIM_MCR_MR2R	0x080		// Reset counter on match 2
#define	TIM_MCR_MR2S	0x100		// Stop prescaler & counter on match 2
#define	TIM_MCR_MR3I	0x200		// IRQ on match 3
#define	TIM_MCR_MR3R	0x400		// Reset counter on match 3
#define	TIM_MCR_MR3S	0x800		// Stop prescaler & counter on match 3

/*
*	Definitions for the CCR register
*/

#define	TIM_CCR_CAP0RE	0x001		// Capture 0 on rising edge
#define	TIM_CCR_CAP0FE	0x002		// Capture 0 on falling edge
#define	TIM_CCR_CAP0I	0x004		// Capture 0 generates interrupt
#define	TIM_CCR_CAP1RE	0x008		// Capture 1 on rising edge
#define	TIM_CCR_CAP1FE	0x010		// Capture 1 on falling edge
#define	TIM_CCR_CAP1I	0x020		// Capture 1 generates interrupt
#define	TIM_CCR_CAP2RE	0x040		// Capture 2 on rising edge
#define	TIM_CCR_CAP2FE	0x080		// Capture 2 on falling edge
#define	TIM_CCR_CAP2I	0x100		// Capture 2 generates interrupt
#define	TIM_CCR_CAP3RE	0x200		// Capture 3 on rising edge
#define	TIM_CCR_CAP3FE	0x400		// Capture 3 on falling edge
#define	TIM_CCR_CAP3I	0x800		// Capture 3 generates interrupt

/*
*	Definitions for the emr register
*/

#define	TIM_EMR_EM0		0x001		// Channel 0 match controls its pin
#define	TIM_EMR_EM1		0x002		// Channel 1 match controls its pin
#define	TIM_EMR_EM2		0x004		// Channel 2 match controls its pin
#define	TIM_EMR_EM3		0x008		// Channel 3 match controls its pin
#define	TIM_EMR_EMC0M	0x030		// Channel 0 activity mask
#define	TIM_EMR_EMC0(n) ((n)<<4)	// Channel 0 activity on match
#define	TIM_EMR_EMC1M	0x0c0		// Channel 1 activity mask
#define	TIM_EMR_EMC1(n) ((n)<<6)	// Channel 1 activity on match
#define	TIM_EMR_EMC2M	0x300		// Channel 2 activity mask
#define	TIM_EMR_EMC2(n) ((n)<<8)	// Channel 2 activity on match
#define	TIM_EMR_EMC3M	0xc00		// Channel 3 activity mask
#define	TIM_EMR_EMC3(n) ((n)<<10)	// Channel 3 activity on match

#define	TIM_EMC_NOP		0			// No action
#define	TIM_EMC_CLR		1			// Clear the pin
#define	TIM_EMC_SET		2			// Set the pin
#define	TIM_EMC_TGL		3			// Toggle the pin

/*
*	Definitions for the PWM control register
*/

#define	TIM_PWMCON_ENA0	0x01		// Enable PWM on channel 0
#define	TIM_PWMCON_ENA1	0x01		// Enable PWM on channel 1
#define	TIM_PWMCON_ENA2	0x01		// Enable PWM on channel 2
#define	TIM_PWMCON_ENA3	0x01		// Enable PWM on channel 3

/*
*	Timer instances, 32-bit timers
*/

static volatile struct lpc210x_tim * const lpc_tim0 = (void *) 0xe0004000;
static volatile struct lpc210x_tim * const lpc_tim1 = (void *) 0xe0008000;

/*
*	Timer instances, 16-bit timers
*/

static volatile struct lpc210x_tim * const lpc_tim2 = (void *) 0xe0070000;
static volatile struct lpc210x_tim * const lpc_tim3 = (void *) 0xe0074000;

#endif

