/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC23xx MMC/SD card controller			*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~			*/
/*																			*/
/*	2010 Mar	ZK		Original											*/
/*	2010 May	ZK		Modified to match NXP's names						*/
/*																			*/
/****************************************************************************/

#ifndef _LPC23XX_MCI
#define _LPC23XX_MCI

struct lpc23xx_mci {

	unsigned power;					// 000 Power control
	unsigned clock;					// 004 Clock control
	unsigned argument;				// 008 Command argument
	unsigned command;				// 00c Command to sent to the card
	unsigned respcmd;				// 010 Command response from the card
	unsigned response[ 4 ];			// 014 Response parameters
	unsigned datatimer;				// 024 Data timeout register
	unsigned datalength;			// 028 Data length
	unsigned datactrl;				// 02c Data control
	unsigned datacnt;				// 030 Data counter
	unsigned stat;					// 034 MCI status bits
	unsigned clr;					// 038 MCI status bit clear control
	unsigned mask0;					// 03c Interrupt mask
	unsigned _1[2];
	unsigned fifocnt;				// 048 FIFO counter
	unsigned _2[13];
	unsigned fifo[ 16 ];			// 080 Data FIFO, same reg 16 times
};

/*
*	Definitions for the power control register
*/
#define	MCI_POWER_CTRL			0x03	// Power control mask
#define	MCI_POWER_CTRL_PWOF		0x00	// Power is off
#define	MCI_POWER_CTRL_PWUP		0x02	// Powering up
#define	MCI_POWER_CTRL_PWON		0x03	// Power is on
#define	MCI_POWER_MCTP			0x00	// MCI CMD pin is totem-pole
#define	MCI_POWER_OPENDRAIN		0x40	// MCI CMD pin is open collector
#define	MCI_POWER_ROD			0x80	// ROD control

/*
*	Definitions for the clock control register
*/

#define	MCI_CLOCK_CDIV(n)	(n)			// Clock divider
#define	MCI_CLOCK_ENABLE	0x0100		// MCI bus clock enable
#define	MCI_CLOCK_PWRSAVE	0x0200		// Power save mode enabled
#define	MCI_CLOCK_BYPASS	0x0400		// MCI bus clock bypasses divider
#define	MCI_CLOCK_WIDEBUS	0x0800		// Enable wide (4-bit) bus mode

/*
*	Definitions for the command register
*/

#define	MCI_COMMAND_INDEX(n)	(n)		// Command index (6 bits)
#define	MCI_COMMAND_RESPONSE	0x040	// Wait for a response
#define	MCI_COMMAND_LONGRSP		0x080	// Long response
#define	MCI_COMMAND_INTERRUPT	0x100	// Wait for interrupt request
#define	MCI_COMMAND_PENDING		0x200	// Wait for CmdPend before sending
#define	MCI_COMMAND_ENABLE		0x400	// Enable command state machine

/*
*	Definitions for the data control register
*/

#define	MCI_DATACTRL_ENABLE		0x01	// Data transfer enabled
#define	MCI_DATACTRL_DIRECTION	0x02	// Data from card to MCI
#define	MCI_DATACTRL_MODE		0x04	// Block(0) or stream(1) transfer mode
#define	MCI_DATACTRL_DMAENABLE	0x08	// Enable DMA
#define	MCI_DATACTRL_BLOCKSIZE(n) ((n)<<7)	// Block size (2^n, n<12)

/*
*	Definitions for the status, mask0 and clr registers
*	For the clr register only the lower 11 bits can be used (up to
*	and including DATDONE).
*/

#define	MCI_CMDCRCFAIL		0x000001	// Command CRC error
#define	MCI_DATACRCFAIL		0x000002	// Data CRC error
#define	MCI_CMDTIMEOUT		0x000004	// Command response timeout
#define	MCI_DATATIMEOUT		0x000008	// Data timeout
#define	MCI_TXUNDERRUN		0x000010	// Transmit underrun
#define	MCI_RXOVERRUN		0x000020	// Receive overrun
#define	MCI_CMDRESPEND		0x000040	// Command response received OK
#define	MCI_CMDSENT			0x000080	// Command sent, no resp. expected
#define	MCI_DATAEND			0x000100	// Data counter is 0
#define	MCI_STARTBITERR		0x000200	// Wide bus start bit error
#define	MCI_DATABLOCKEND	0x000400	// Data transfer succeeded
#define	MCI_CMDACTIVE		0x000800	// Command transfer in progress
#define	MCI_TXACTIVE		0x001000	// Transmission in progress
#define	MCI_RXACTIVE		0x002000	// Reception in progress
#define	MCI_TXFIFOHALFEMPTY	0x004000	// Transmit FIFO half empty
#define	MCI_RXFIFOHALFFULL	0x008000	// Receive FIFO half full
#define	MCI_TXFIFOFULL		0x010000	// Transmit FIFO full
#define	MCI_RXFIFOFULL		0x020000	// Receive FIFO full
#define	MCI_TXFIFOEMPTY		0x040000	// Transmit FIFO empty
#define	MCI_RXFIFOEMPTY		0x080000	// Receive FIFO empty
#define	MCI_TXDATAAVLBL		0x100000	// Data available in transmit FIFO
#define	MCI_RXDATAAVVLBL	0x200000	// Data available in receive FIFO

/*
*	MCI instance
*/

static volatile struct lpc23xx_mci * const lpc_mci = (void *) 0xe008c000;

#endif

