/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC23xx pulse width modulator module	*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	*/
/*																			*/
/*	2010 Mar	ZK		Original											*/
/*	2010 May	ZK		Modified to match NXP's names						*/
/*																			*/
/****************************************************************************/

#ifndef _LPC23XX_EMC
#define _LPC23XX_EMC

/*
*	LPC23xx pulse width modulator registers
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/

struct	lpc23xx_pwm {

	unsigned ir;				// Interrupt reg
	unsigned tcr;				// Timer control
	unsigned tc;				// Free-running counter
	unsigned pr;				// Prescaler upper count value
	unsigned pc;				// Prescaler counter clocked from PCLK
	unsigned mcr;				// Match control
	unsigned mr0;				// Match register 0
	unsigned mr1;				// Match register 1
	unsigned mr2;				// Match register 2
	unsigned mr3;				// Match register 3
	unsigned ccr;				// Capture control register
	unsigned cr0;				// Capture register 0
	unsigned cr1;				// Capture register 0
	unsigned cr2;				// Capture register 0
	unsigned cr3;				// Capture register 0
	unsigned _;
	unsigned mr4;				// Match register 4
	unsigned mr5;				// Match register 5
	unsigned mr6;				// Match register 6
	unsigned pcr;				// PWM control
	unsigned ler;				// Load enable
	unsigned ctcr;				// Count control
};

/*
*	Definitions for the interrupt control register
*/

#define	PWM_IR_MR0		0x001		// Interrupt flag for match 0
#define	PWM_IR_MR1		0x002		// Interrupt flag for match 1
#define	PWM_IR_MR2		0x004		// Interrupt flag for match 2
#define	PWM_IR_MR3		0x008		// Interrupt flag for match 3
#define	PWM_IR_CAP0		0x010		// Interrupt flag for capture 0
#define	PWM_IR_CAP1		0x020		// Interrupt flag for capture 1
#define	PWM_IR_MR4		0x100		// Interrupt flag for match 4
#define	PWM_IR_MR5		0x200		// Interrupt flag for match 5
#define	PWM_IR_MR6		0x400		// Interrupt flag for match 6

/*
*	Definitions for the timer control register
*/

#define	PWM_TCR_COUNTER_ENABLE	0x01	// Counter is enabled
#define	PWM_TCR_COUNTER_RESET	0x02	// Counter and prescaler held in reset
#define	PWM_TCR_PWM_ENABLE		0x08	// PWM mode is enabled

/*
*	Definitions for the count control register
*/

#define	PWM_CTCR_PCLK	0x00		// Counter counts PCLK
#define	PWM_CTCR_RISE	0x01		// Counter counts rising edges of CAP
#define	PWM_CTCR_FALL	0x02		// Counter counts falling edges of CAP
#define	PWM_CTCR_BOTH	0x03		// Counter counts both edges of CAP
#define	PWM_CTCR_CAP0	0x00		// CAP is from channel capture input 0
#define	PWM_CTCR_CAP1	0x04		// CAP is from channel capture input 1

/*
*	Definitions for the match control register
*/

#define	PWM_MCR_MR0I	0x000001	// IRQ on match 0
#define	PWM_MCR_MR0R	0x000002	// Reset counter on match 0
#define	PWM_MCR_MR0S	0x000004	// Stop prescaler & counter on match 0
#define	PWM_MCR_MR1I	0x000008	// IRQ on match 1
#define	PWM_MCR_MR1R	0x000010	// Reset counter on match 1
#define	PWM_MCR_MR1S	0x000020	// Stop prescaler & counter on match 1
#define	PWM_MCR_MR2I	0x000040	// IRQ on match 2
#define	PWM_MCR_MR2R	0x000080	// Reset counter on match 2
#define	PWM_MCR_MR2S	0x000100	// Stop prescaler & counter on match 2
#define	PWM_MCR_MR3I	0x000200	// IRQ on match 3
#define	PWM_MCR_MR3R	0x000400	// Reset counter on match 3
#define	PWM_MCR_MR3S	0x000800	// Stop prescaler & counter on match 3
#define	PWM_MCR_MR4I	0x001000	// IRQ on match 4
#define	PWM_MCR_MR4R	0x002000	// Reset counter on match 4
#define	PWM_MCR_MR4S	0x004000	// Stop prescaler & counter on match 4
#define	PWM_MCR_MR5I	0x008000	// IRQ on match 5
#define	PWM_MCR_MR5R	0x010000	// Reset counter on match 5
#define	PWM_MCR_MR5S	0x020000	// Stop prescaler & counter on match 5
#define	PWM_MCR_MR6I	0x040000	// IRQ on match 6
#define	PWM_MCR_MR6R	0x080000	// Reset counter on match 6
#define	PWM_MCR_MR6S	0x100000	// Stop prescaler & counter on match 6

/*
*	Definitions for the capture control register
*/

#define	PWM_CCR_CRE0	0x001		// Capture 0 on rising edge
#define	PWM_CCR_CFE0	0x002		// Capture 0 on falling edge
#define	PWM_CCR_IRQ0	0x004		// Capture 0 generates interrupt
#define	PWM_CCR_CRE1	0x008		// Capture 1 on rising edge
#define	PWM_CCR_CFE1	0x010		// Capture 1 on falling edge
#define	PWM_CCR_IRQ1	0x020		// Capture 1 generates interrupt
#define	PWM_CCR_CRE2	0x040		// Capture 2 on rising edge
#define	PWM_CCR_CFE2	0x080		// Capture 2 on falling edge
#define	PWM_CCR_IRQ2	0x100		// Capture 2 generates interrupt
#define	PWM_CCR_CRE3	0x200		// Capture 3 on rising edge
#define	PWM_CCR_CFE3	0x400		// Capture 3 on falling edge
#define	PWM_CCR_IRQ3	0x800		// Capture 3 generates interrupt

/*
*	Definitions for the PWM control register
*/

#define	PWM_PCR_SEL2	0x0004		// Double edge mode for PWM2
#define	PWM_PCR_SEL3	0x0008		// Double edge mode for PWM3
#define	PWM_PCR_SEL4	0x0010		// Double edge mode for PWM4
#define	PWM_PCR_SEL5	0x0020		// Double edge mode for PWM5
#define	PWM_PCR_SEL6	0x0040		// Double edge mode for PWM6
#define	PWM_PCR_ENA1	0x0200		// Enable PWM1
#define	PWM_PCR_ENA2	0x0400		// Enable PWM2
#define	PWM_PCR_ENA3	0x0800		// Enable PWM3
#define	PWM_PCR_ENA4	0x1000		// Enable PWM4
#define	PWM_PCR_ENA5	0x2000		// Enable PWM5
#define	PWM_PCR_ENA6	0x4000		// Enable PWM6

/*
*	Definitions for the latch enable register
*/

#define PWM_LER_EM0L	0x01		// Enable match 0 latch
#define PWM_LER_EM1L	0x02		// Enable match 1 latch
#define PWM_LER_EM2L	0x04		// Enable match 2 latch
#define PWM_LER_EM3L	0x08		// Enable match 3 latch
#define PWM_LER_EM4L	0x10		// Enable match 4 latch
#define PWM_LER_EM5L	0x20		// Enable match 5 latch
#define PWM_LER_EM6L	0x40		// Enable match 6 latch

static volatile struct lpc23xx_pwm * const lpc_pwm = (void *) 0xe0018000;

#endif

