/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC210x A/D converter module			*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~			*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC23xx version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210X_ADC
#define _LPC210X_ADC

/*
*	A/D controller registers
*/

struct lpc210x_adc {

	unsigned cr;						// 000 Control register
	unsigned gdr;						// 004 Conversion result
	unsigned _;
	unsigned inten;						// 00c Interrupt enable register
	unsigned dr[ 8 ];					// 010 Conversion results
	unsigned stat;						// 030 Status register
};

/*
*	Control register
*/

#define	ADC_CR_SEL			0x000000FF	// Channel select mask
#define	ADC_CR_CLKDIV		0x0000FF00	// Clock divider mask
#define	ADC_CR_CLKDIV_SET(x) ((x)<<8)	// Clock divider
#define	ADC_CR_BURST		0x00010000	// Burst mode select
#define	ADC_CR_CLKS			0x000e0000	// Clocks mask
#define	ADC_CR_CLKS_10		0x00000000	// 10 bits accuracy
#define	ADC_CR_CLKS_9		0x00020000	//  9 bits accuracy
#define	ADC_CR_CLKS_8		0x00040000	//  8 bits accuracy
#define	ADC_CR_CLKS_7		0x00060000	//  7 bits accuracy
#define	ADC_CR_CLKS_6		0x00080000	//  6 bits accuracy
#define	ADC_CR_CLKS_5		0x000a0000	//  5 bits accuracy
#define	ADC_CR_CLKS_4		0x000c0000	//  4 bits accuracy
#define	ADC_CR_CLKS_3		0x000e0000	//  3 bits accuracy
#define	ADC_CR_PDN			0x00200000	// Power down (1:powered 0:off)
#define	ADC_CR_START		0x07000000	// Conversion start control mask
#define	ADC_CR_START_IDLE	0x00000000	// A/D halted
#define	ADC_CR_START_NOW	0x01000000	// Start now
#define	ADC_CR_START_EINT0	0x02000000	// Start on EINT0 edge
#define	ADC_CR_START_PORT22	0x03000000	// Start on timer P0.22 edge
#define	ADC_CR_START_MAT01	0x04000000	// Start on timer 0 OC 1 edge
#define	ADC_CR_START_MAT03	0x05000000	// Start on timer 0 OC 3 edge
#define	ADC_CR_START_MAT10	0x06000000	// Start on timer 1 OC 0 edge
#define	ADC_CR_START_MAT11	0x07000000	// Start on timer 1 OC 1 edge
#define	ADC_CR_EDGE			0x08000000	// Start on falling(1) or rising(0) edge

/*
*	Conversion result register
*/

#define	ADC_GDR_RES			0x0000FFC0	// Result mask
#define	ADC_GDR_RES_SFT		6			// Result shift right amount
#define	ADC_GDR_CHN			0x07000000	// Channel select mask
#define	ADC_GDR_CHN_SFT		24			// Channel select right shift
#define	ADC_GDR_OVERRUN		0x40000000	// Channel overrun
#define	ADC_GDR_DONE		0x80000000	// Conversion is done

/*
*	Interrupt enable register
*/

#define	ADC_INTEN_INTEN		0x0ff		// Per-channel IRQ enable mask
#define	ADC_INTEN_INTEN_CH(n) (1<<(n))	// Enable IRQ for channel n
#define	ADC_INTEN_GINTEN	0x100		// DONE generates IRQ

/*
*	Result data registers
*/

#define	ADC_DR_RES			0x0000FFC0	// Result mask
#define	ADC_DR_RES_SFT		6			// Result shift right amount
#define	ADC_DR_CHN			0x07000000	// Channel select mask
#define	ADC_DR_CHN_SFT		24			// Channel select right shift
#define	ADC_DR_OVERRUN		0x40000000	// Channel overrun
#define	ADC_DR_DONE			0x80000000	// Conversion is done

/*
*	Status register
*/

#define	ADC_STAT_DONE		 0x000FF	// 8 bits indicating ch done
#define	ADC_STAT_DONE_SFT	 0			// Shift amount for done
#define	ADC_STAT_OVERRUN	 0x0FF00	// 8 bits indicating ch overrun
#define	ADC_STAT_OVERRUN_SFT 8			// Shift amount for overrun
#define	ADC_STAT_ADINT		 0x10000	// Interrupt is pending

/*
*	A/D instance
*/

static volatile struct lpc210x_adc * const lpc_adc = (void *) 0xe0034000;

#endif

