/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the Philips LPC210x interrupt controller		*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~		*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC23xx version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210X_VIC
#define _LPC210X_VIC

/*
*	LPC2378 vectored interrupt controller registers
*/

struct lpc210x_vic {

	unsigned irqstat;				// 000 Interrupt status
	unsigned fiqstat;				// 004 Fast interrupt status
	unsigned rawintr;				// 008 Raw interrupt status
	unsigned intselect;				// 00c Select fast interrupt
	unsigned intenable;				// 010 Interrupt enable
	unsigned intenclr;				// 014 Enable clear
	unsigned softint;				// 018 Soft interrupt request
	unsigned softintclr;			// 01c Soft request clear
	unsigned protection;			// 020 User/supervisor access select
	unsigned _1[3];
	void	 (*vectaddr)(void);		// 030 Address of next ISR to service
	void	 (*defvectadr)(void);	// 034 Default vector
	unsigned _2[50];
	void	 (*vectaddr[16])(void);	// 100 Vectored IRQ addresses
	unsigned _3[48];
	unsigned vectcntl[16];			// 200 Vector contol
};

/*
*	Definitions for the protection register
*/

#define	VIC_PROTECTION_USR	0			// Access allowed from user mode
#define	VIC_PROTECTION_SUP	1			// Supervisor address only

/*
*	Interrupt sources
*/

#define	VIC_WDT			0				// Watchdog timer
#define	VIC_SWI			1				// Software interrupt
#define	VIC_ICE_RX		2				// Embedded ICE receive
#define	VIC_ICE_TX		3				// Embedded ICE transmit
#define	VIC_TIM0		4				// Timer 0
#define	VIC_TIM1		5				// Timer 1
#define	VIC_SIO0		6				// Serial port 0
#define	VIC_SIO1		7				// Serial port 1
#define	VIC_I2C0		9				// I2C bus controller 0
#define	VIC_SPI			10				// SPI controller and SSP 0	shared
#define	VIC_SSP			11				// SSP controller 1
#define	VIC_PLL			12				// PLL lock
#define	VIC_RTC			13				// Real-time clock
#define	VIC_EXT0		14				// External interrupt 0
#define	VIC_EXT1		15				// External interrupt 1
#define	VIC_EXT2		16				// External interrupt 2
#define	VIC_ADC			18				// Analog to digital converter
#define	VIC_I2C1		19				// I2C bus controller 1
#define	VIC_TIM2		26				// Timer 2
#define	VIC_TIM3		27				// Timer 3

/*
*	Definitions for the vector control registers
*/

#define	VIC_VECTCNTL_REQ(n)		(n)		// The request assigned to the slot
#define	VIC_VECTCNTL_ENA		0x20	// The slot is enabled

/*
*	VIC instance
*/

static volatile struct lpc210x_vic * const lpc_vic = (void *) 0xfffff000;

#endif

