/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC23xx OTG controller module			*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~			*/
/*																			*/
/*	2010 Mar	ZK		Original											*/
/*	2010 May	ZK		Modified to match NXP's names						*/
/*																			*/
/****************************************************************************/

#ifndef _LPC23XX_OTG
#define _LPC23XX_OTG

/*
*	OTG controller registers
*/

struct lpc23xx_otg {

	unsigned		_1[64];
	unsigned		intst;				// R	Interrupt status			100
	unsigned		inten;				// RW	Interrupt enable			104
	unsigned		intset;				// W	Interrupt set				108
	unsigned		intclr;				// W	Interrupt clear				10c

	unsigned		stctrl;				// RW	Status and control			110
	unsigned		tmr;				// RW	Timer control				114
	unsigned		_2[122];
	union
	{
		unsigned	i2crx;				// R	I2C data FIFO access		300
		unsigned	i2ctx;				// W	I2C data FIFO access		300
	};
	unsigned		i2csts;				// R	I2C status					304
	unsigned		i2cctl;				// R	I2C control					308
	unsigned		i2cclkhi;			// R	I2C clock high timer		30c
	unsigned		i2cclklo;			// R	I2C clock low timer			310
	unsigned		_3[824];
	unsigned		clkctrl;			// RW	Clock control				ff4
	unsigned		clkst;				// R	Clock status				ff8
};

/*
*	Definitions for the intst, inten, intset, intclr registers
*/

#define	OTG_INT_TMR				0x01	// Time-out interrupt
#define	OTG_INT_REMOVE_PU		0x02	// Remove pull-up interrupt
#define	OTG_INT_HNP_FAILURE		0x04	// HNP failed
#define	OTG_INT_HNP_SUCCESS		0x08	// HNP succeeded

/*
*	Definitions for the stctrl register
*/

#define	OTG_STCTRL_PORT_FUNC	0x003	// Port function control mask
#define	OTG_STCTRL_TMR_SCALE	0x00c	// Timer scale mask
#define	OTG_STCTRL_TMR_SCALE_10	 	0	// Timer scale 10us
#define	OTG_STCTRL_TMR_SCALE_100	4	// Timer scale 100us
#define	OTG_STCTRL_TMR_SCALE_1000	8	// Timer scale 1000us
#define	OTG_STCTRL_TMR_MODE		0x010	// Timer mode (0:mono 1:free)
#define	OTG_STCTRL_TMR_EN		0x020	// Timer enable
#define	OTG_STCTRL_TMR_RST		0x040	// Timer reset
#define	OTG_STCTRL_B_HNP_TRACK	0x100	// Enable HNP tracking for dev B
#define	OTG_STCTRL_A_HNP_TRACK	0x200	// Enable HNP tracking for dev B
#define	OTG_STCTRL_PU_REMOVED	0x800	// Pull-up removed
#define	OTG_STCTRL_TMR_CNT_M 0xffff0000	// Timer count mask
#define	OTG_STCTRL_TMR_CNT_S 	16		// Timer count shift

#define	OTG_PORT_FUNC_U1D_U2H	0		// U1: device (OTG) U2: host
#define	OTG_PORT_FUNC_U1H_U2H	1		// U1: host (OTG) U2: host
#define	OTG_PORT_FUNC_U1H_U2D	2		// U1: host U2: device

/*
*	Definitions for the clkctrl and clkst  registers
*/

#define	OTG_CLK_HOST		0x01	// Host clock
#define	OTG_CLK_DEV			0x02	// Device clock
#define	OTG_CLK_I2C			0x04	// I2C clock
#define OTG_CLK_OTG			0x08	// OTG clock
#define	OTG_CLK_AHB			0x10	// AHB clock

/*
*	Definitions for the i2ctx register (lower 8 bits are the data)
*/

#define	OTG_I2CTX_START		0x100	// Send a start before the byte
#define	OTG_I2CTX_STOP		0x200	// Send a stop after the byte

/*
*	Definitions for the i2csts register
*/

#define OTG_I2CSTS_TDI		0x001	// Transaction done interrupt
#define OTG_I2CSTS_AFI		0x002	// Arbitration failure interrupt
#define OTG_I2CSTS_NAI		0x004	// No ACK interrupt
#define OTG_I2CSTS_DRMI		0x008	// Master data request interrupt
#define OTG_I2CSTS_DRSI		0x010	// Slave data request interrupt
#define OTG_I2CSTS_ACTIVE	0x020	// Bus is busy
#define OTG_I2CSTS_SCL		0x040	// Current value of SCL
#define OTG_I2CSTS_SDA		0x080	// Current value of SDA
#define OTG_I2CSTS_RFF		0x100	// Receive FIFO full
#define OTG_I2CSTS_RFE		0x200	// Receive FIFO empty
#define OTG_I2CSTS_TFF		0x400	// Transmit FIFO full
#define OTG_I2CSTS_TFE		0x800	// Transmit FIFO empty

/*
*	Definitions for the i2cctl register
*/

#define	OTG_I2CCTL_TDIE		0x001	// Enable TD interrupt
#define	OTG_I2CCTL_AFIE		0x002	// Enable AF interrupt
#define	OTG_I2CCTL_NAIE		0x004	// Enable NA interrupt
#define	OTG_I2CCTL_DRMIE	0x008	// Enable DRM interrupt
#define	OTG_I2CCTL_DRSIE	0x010	// Enable DRS interrupt
#define	OTG_I2CCTL_REFIE	0x020	// Enable RFF interrupt
#define	OTG_I2CCTL_RFDAIE	0x040	// Enable !RFE interrupt
#define	OTG_I2CCTL_TFFIE	0x080	// Enable !TFF interrupt
#define	OTG_I2CCTL_SRST		0x100	// Soft reset

/*
*	OTG instance
*/

static volatile struct lpc23xx_otg * const lpc_otg = (void *) 0xffe0c000;

#endif
