/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC210x watchdog timer					*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~					*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC23xx version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210X_WDT
#define _LPC210X_WDT

/*
*	LPC2378 watchdog registers
*/

struct lpc210x_wdt {

	unsigned mod;					// 000 Watchdog operation mode
	unsigned tc;					// 004 Timeout constant ( >= 0x000000ff )
	unsigned feed;					// 008 Feed the watchdog or it barks!
	unsigned tv;					// 00c Momentarily value of the counter
};

/*
*	Definitions for the mode register
*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*	The WDEN and WDRESET bits can only be set, they can not be cleared.
*	If you set the WDEN bit alone then the watchdog will requests for an
*	interrupt when it expires.
*	If you also set the WDRESET bit, then when the timer expires, the CPU
*	will be reset.
*/

#define	WDT_MOD_WDEN	0x01		// Watchdog is enabled
#define	WDT_MOD_WDRESET	0x02		// Watchdog resets chip when expires
#define	WDT_MOD_WDTOF	0x04		// Time-out flag (indicates WD reset)
#define	WDT_MOD_WDTINT	0x08		// Interrupt request (read-only)

/*
*	Definitions for the feed register
*
*	VERY IMPORTANT:
*		You have to write these two values without any intervening access to
*		any other watchdog registers. If there's *any* peripheral bus activity
*		*including a DMA cycle* between the two feed writes, you will get a
*		watchdog reset immediately.
*
*		The only safe way to feed the watchdog is:
*		- Disable both IRQ and FIQ
*		- Stop the general purpose DMA (if it's running a peripheral xfer)
*		- Feed the watchdog
*		- Restart the DMA engine (if needed)
*		- Re-enable interrupts
*/

#define	WDT_FEED_FOOD1	0xaa
#define	WDT_FEED_FOOD2	0x55

/*
*	Watchdog instance
*/

static volatile struct lpc210x_wdt * const lpc_wdt = (void *) 0xe0000000;

#endif

