/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the NXP LPC210x I2C controller					*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~					*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC23xx version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210X_I2C
#define _LPC210X_I2C

/*
*	I2C controller registers
*	~~~~~~~~~~~~~~~~~~~~~~~~
*/

struct	lpc210x_i2c {

	unsigned conset;				// Control register	set register
	unsigned stat;					// Status register
	unsigned dat;					// Data register
	unsigned adr;					// Slave address register
	unsigned sclh;					// SCH duty cycle high period (16 bits)
	unsigned scll;					// SCH duty cycle low period (16 bits)
	unsigned conclr;				// Control register clear register
};

/*
*	Definitions for contorl set/clear registers
*	Writing a '1' bit to the conset register will set the bit in the
*	control register, writing a '1' bit to the conclr register will clear
*	the bit in the control register. Writing a '0' bit to either register
*	has no effect.
*	Reading the current state of the control register is done by reading
*	the conset register. The conclr register is write only.
*/

#define	I2C_CON_I2EN	0x40		// I2C interface enabled
#define	I2C_CON_STA		0x20		// Start flag (enter master mode)
#define	I2C_CON_STO		0x10		// Stop flag (cleared by HW)
#define	I2C_CON_SI		0x08		// Interrupt flag (set by HW)
#define	I2C_CON_AA		0x04		// Assert acknowledge

/*
*	Definitions for the status register
*	It encodes the state of the I2C state machine.
*	The 5 state groups are the following:
*	_MT_	Master transmitter
*	_MR_	Master receiver
*	_ST_	Slave transmitter
*	_SR_	Slave receiver
*	_MI_	Miscellaneous
*/

#define	I2C_STAT_MT_STA		0x08	// Start condition has been transmitted
#define	I2C_STAT_MT_REP		0x10	// Repeated start has been transmitted
#define	I2C_STAT_MT_AACK	0x18	// Addr had been sent, ACK was received
#define	I2C_STAT_MT_ANAK	0x20	// Addr had been sent, NAK was received
#define	I2C_STAT_MT_DACK	0x28	// Data had been sent, ACK was received
#define	I2C_STAT_MT_DNAK	0x30	// Data had been sent, NAK was received
#define	I2C_STAT_MT_ARBL	0x38	// Arbitration was lost

#define	I2C_STAT_MR_STA		0x08	// Start transmitted
#define	I2C_STAT_MR_REP		0x10	// Repeated start transmitted
#define	I2C_STAT_MR_ARBL	0x38	// Arbitration lost
#define	I2C_STAT_MR_AACK	0x40	// Addr sent, ACK received
#define	I2C_STAT_MR_ANAK	0x48	// Addr sent, NAK received
#define	I2C_STAT_MR_DACK	0x50	// Data received, ACK sent
#define	I2C_STAT_MR_DNAK	0x58	// Data received, ACK sent

#define	I2C_STAT_ST_AACK	0xa8	// Addr received, ACK sent
#define	I2C_STAT_ST_LACK	0xb0	// Lost mastership, addr rec'd ACK sent
#define	I2C_STAT_ST_DACK	0xb8	// Data byte sent, ACK received
#define	I2C_STAT_ST_DNAK	0xc0	// Data byte sent, NAK received
#define	I2C_STAT_ST_LDACK	0xc8	// Last data byte sent, ACK received

#define	I2C_STAT_SR_AACK	0x60	// Addr received, ACK sent
#define	I2C_STAT_SR_LACK	0x68	// Lost mastership, addr rec'd ACK sent
#define	I2C_STAT_SR_AGACK	0x70	// B'cast addr received, ACK sent
#define	I2C_STAT_SR_LGACK	0x78	// Lost master, b'cast rec'd ACK sent
#define	I2C_STAT_SR_DACK	0x80	// Data byte received, ACK sent
#define	I2C_STAT_SR_DNAK	0x88	// Data byte received, NAK sent
#define	I2C_STAT_SR_DGACK	0x90	// B'cast data byte received, ACK sent
#define	I2C_STAT_SR_DGNAK	0x98	// B'cast data byte received, NAK sent
#define	I2C_STAT_SR_STOP	0xa0	// STOP or repeated START received

#define	I2C_STAT_MI_WAIT	0xf8	// Status info is not yet ready
#define	I2C_STAT_MI_BERR	0x00	// A bus error occurred

/*
*	Definitions for the address register
*/

#define	I2C_ADR_GCALL		0x01	// General call (broadcast) enable
#define	I2C_ADR_MASK		0xfe	// Slave address

/*
*	I2C instances
*/

static volatile struct lpc210x_i2c * const lpc_i2c0 = (void *) 0xe001c000;
static volatile struct lpc210x_i2c * const lpc_i2c1 = (void *) 0xe005c000;

#endif

