/****************************************************************************/
/* Copyright 2010, © Bendor Research Pty. Ltd. All rights reserved.			*/
/* Permission is granted to use this software for any purpose whatsoever	*/
/* as long as this copyright notice is preserved. The code is provided		*/
/* "as is", with no explicit, implicit or implied warranty or guarantee		*/
/* of any kind and Bendor Research Pty. Ltd. can not be held liable for		*/
/* any loss or damages arising out of the use of this software.				*/
/****************************************************************************/
/*																			*/
/*	Include file describing the Philips LPC210x SSP controllers				*/
/*	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~				*/
/*																			*/
/*	2011 Jan	ZK		Generated from the LPC210x version					*/
/*																			*/
/****************************************************************************/

#ifndef _LPC210X_SSP
#define _LPC210X_SSP

/*
*	LPC210x SSP controller registers
*/

struct lpc210x_ssp {

	unsigned cr0;					// Control register	0
	unsigned cr1;					// Control register	1
	unsigned dr;					// Data register
	unsigned sr;					// Status register
	unsigned cpsr;					// Clock prescaler register
	unsigned imsc;					// Interrupt mask set/clear
	unsigned ris;					// Raw interrupt status
	unsigned mis;					// Masked interrupt status
	unsigned icr;					// Interrupt clear
	unsigned _[23];
	unsigned tcr;					// Test control register
	unsigned itip;					// Integration test input register
	unsigned itop;					// Integration test output register
	unsigned tdr;					// Test data register
};

/*
*	Definitions for control register 0
*/

#define	SSP_CR0_DSS			0x000f	// Data size select mask
#define	SSP_CR0_DSS_16		0x000f	// Word length is 16 bits
#define	SSP_CR0_DSS_15		0x000e	// Word length is 15 bits
#define	SSP_CR0_DSS_14		0x000d	// Word length is 14 bits
#define	SSP_CR0_DSS_13		0x000c	// Word length is 13 bits
#define	SSP_CR0_DSS_12		0x000b	// Word length is 12 bits
#define	SSP_CR0_DSS_11		0x000a	// Word length is 11 bits
#define	SSP_CR0_DSS_10		0x0009	// Word length is 10 bits
#define	SSP_CR0_DSS_9		0x0008	// Word length is  9 bits
#define	SSP_CR0_DSS_8		0x0007	// Word length is  8 bits
#define	SSP_CR0_DSS_7		0x0006	// Word length is  7 bits
#define	SSP_CR0_DSS_6		0x0005	// Word length is  6 bits
#define	SSP_CR0_DSS_5		0x0004	// Word length is  5 bits
#define	SSP_CR0_DSS_4		0x0003	// Word length is  4 bits
#define	SSP_CR0_FRF			0x0030	// Frame format mask
#define	SSP_CR0_FRF_SPI		0x0000	// SPI (Motorola)
#define	SSP_CR0_FRF_TI		0x0010	// SSI (Texas Intruments)
#define	SSP_CR0_FRF_MWI		0x0020	// Microwire (National Semiconductors)
#define	SSP_CR0_CPOL		0x0040	// Clock polarity (SPI only)
#define	SSP_CR0_CPHA		0x0080	// Clock phase (SPI only)
#define	SSP_CR0_SCR			0xff00	// Prescaler mask
#define	SSP_CR0_SCR_SET(x) (((x)-1)<<8)	// Prescaler set

/*
*	Definitions for control register 1
*/

#define	SSP_CR1_LBM			0x01	// Loop-back mode
#define	SSP_CR1_SSE			0x02	// SSP is enabled
#define	SSP_CR1_MS			0x00	// Master/slave mode (0:master)
#define	SSP_CR1_SOD			0x08	// Slave output disable

/*
*	Definitions for the status register
*/

#define	SSP_SR_TFE			0x01	// Transmit FIFO is empty
#define	SSP_SR_TNF			0x02	// Transmit FIFO is not full
#define	SSP_SR_RNE			0x04	// Receive FIFO is not empty
#define	SSP_SR_RFF			0x08	// Receive FIFO is full
#define	SSP_SR_BSY			0x10	// SSP is busy

/*
*	Definitions for the interrupt mask set/clear register
*/

#define	SSP_IMSC_RORIM		0x01	// Receive overrun
#define	SSP_IMSC_RTIM		0x02	// Receive timeout
#define	SSP_IMSC_RXIM		0x04	// Receive FIFO half full
#define	SSP_IMSC_TXIM		0x08	// Transmit FIFO half empty

/*
*	Definitions for the raw interrupt status register
*/

#define	SSP_RIS_RORRIS		0x01	// Receive overrun
#define	SSP_RIS_RTRIS		0x02	// Receive timeout
#define	SSP_RIS_RXRIS		0x04	// Receive FIFO half full
#define	SSP_RIS_TXRIS		0x08	// Transmit FIFO half empty

/*
*	Definitions for the masked interrupt status register
*/

#define	SSP_MIS_RORMIS		0x01	// Receive overrun
#define	SSP_MIS_RTMIS		0x02	// Receive timeout
#define	SSP_MIS_RXMIS		0x04	// Receive FIFO half full
#define	SSP_MIS_TXMIS		0x08	// Transmit FIFO half empty

/*
*	Definitions for the interrupt clear register
*/

#define	SSP_ICR_RORIC		0x01	// Receive overrun
#define	SSP_ICR_RTIC		0x02	// Receive timeout

/*
*	Definitions for the test register
*/

#define	SSP_TCR_ITEN		0x01	// Integration test enable
#define	SSP_TCR_TESTFIFO	0x02	// FIFO test enable

/*
*	SSP instances
*/

static volatile struct lpc210x_ssp * const lpc_ssp = (void *) 0xe0068000;

#endif

